Enhanced Serial Communication Interface (eSCI)
MPC5566 Microcontroller Reference Manual, Rev. 2
21-18 Freescale Semiconductor
21.4 Functional Description
21.4.1 Overview
This section provides a complete functional description of the eSCI module, detailing the operation of the
design from the end user perspective in a number of subsections.
Figure 21-11 shows the structure of the eSCI module. The eSCI allows full duplex, asynchronous, NRZ
serial communication between the CPU and remote devices, including other CPUs. The eSCI transmitter
and receiver operate independently, although they use the same baud rate generator. The CPU monitors the
status of the eSCI, writes the data to be transmitted, and processes received data.
Figure 21-11. eSCI Operation Block Diagram
Table 21-14. ESCIx_LPR Field Description
Field Description
0–15
Pn
Polynomial bit x
n
. Bits P15–P0 are used to define the LIN polynomial - standard is x
15
+ x
14
+ x
10
+ x
8
+ x
7
+ x
4
+
x
3
+ 1 (the polynomial used for the CAN protocol).
16–31 Reserved.
eSCI Data
RE
Register
Receive and
Wake-up Control
RWU
LOOPS
RSRC
M
WAKE
ILT
PE
PT
TE
LOOPS
SBK
RSRC
Data Format
Control
Transmit
Control
Transmit
Shift Register
NF
FE
PF
RAF
R8
IDLE
RDRF
OR
ILIE
RIE
BAUD Rate
Generator
Bus
Clock
IRQ to
CPU
TDRE
TC
TIE
TCIE
TXD
÷16
T8
SBR0–SBR12
RXD
SCI Data
Register
Receive
Shift Register
IDLE
IRQ
TC
IRQ
TDRE
IRQ
RDRF/
OR IRQ
To Next Page
Loading...
