Fast Ethernet Controller (FEC)
MPC5566 Microcontroller Reference Manual, Rev. 2
15-42 Freescale Semiconductor
The application must specify the desired pause duration in the OPD register.
Note that when the transmitter is paused due to receiver/microcontroller pause frame detection, transmit
flow control pause (TCR[TFC_PAUSE]) still can be asserted and causes the transmission of a single pause
frame. In this case, the EIR[GRA] interrupt is not asserted.
15.4.11 Inter-Packet Gap (IPG) Time
The minimum inter-packet gap time for back-to-back transmission is 96 bit times. After completing a
transmission or after the backoff algorithm completes, the transmitter waits for carrier sense to be negated
before starting its 96 bit time IPG counter. Frame transmission can begin 96 bit times after carrier sense is
negated if it stays negated for at least 60 bit times. If carrier sense asserts during the last 36 bit times, it is
ignored and a collision occurs.
The receiver receives back-to-back frames with a minimum spacing of at least 28 bit times. If an
inter-packet gap between receive frames is less than 28 bit times, the following frame can be discarded by
the receiver.
15.4.12 Collision Handling
If a collision occurs during frame transmission, the Ethernet controller continues the transmission for at
least 32 bit times, transmitting a JAM pattern consisting of 32 ones. If the collision occurs during the
preamble sequence, the JAM pattern is sent after the end of the preamble sequence.
If a collision occurs within 512 bit times, the retry process is initiated. The transmitter waits a random
number of slot times. A slot time is 512 bit times. If a collision occurs after 512 bit times, then no
retransmission is performed and the end of frame buffer is closed with a late collision (LC) error indication.
15.4.13 Internal and External Loopback
Both internal and external loopback are supported by the Ethernet controller. In loopback mode, both of
the FIFOs are used and the FEC actually operates in a full-duplex fashion. Both internal and external
loopback are configured using combinations of the LOOP and DRT bits in the RCR register and the FDEN
bit in the TCR register.
For both internal and external loopback set FDEN = 1.
For internal loopback set RCR[LOOP] = 1 and RCR[DRT] = 0. FEC_TX_EN and FEC_TX_ER do not
assert during internal loopback. During internal loopback, the transmit/receive data rate is higher than in
normal operation because the internal system clock is used by the transmit and receive blocks instead of
the clocks from the external transceiver. This causes an increase in the required system bus bandwidth for
transmission and the DMA must move data to and from external memory. Pace the frames on the transmit
side or limit the size of the frames to prevent transmit FIFO underrun and receive FIFO overflow.
For external loopback set RCR[LOOP] = 0, RCR[DRT] = 0 and configure the external transceiver for
loopback.
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