NXP Semiconductors MPC5566 - Introduction

MPC5566 Microcontroller Reference Manual, Rev. 2
Freescale Semiconductor 13-1
Chapter 13
Flash Memory
13.1 Introduction
This section provides information about the flash bus interface unit (FBIU) and the flash memory block.
13.1.1 Block Diagram
Figure 13-1 shows a block diagram of the flash memory module. The FBIU is addressed through the
system bus while the flash control and status registers are addressed through the slave (peripheral) bus.
Figure 13-1. Flash System Block Diagram
13.1.2 Overview
The flash module serves as electrically programmable and erasable non-volatile memory (NVM) that is
ideal for program and data storage for single-chip applications allowing for field reprogramming without
requiring external programming voltage sources. The module is a solid-state silicon memory device
consisting of blocks of single-transistor storage elements.
The device flash contains a flash bus interface unit (FBIU) and a flash memory array. The Flash BIU
interfaces the system bus to a dedicated flash memory array controller. The FBIU supports a 64-bit data
bus width at the system bus port, and a 256-bit read data interface from the flash memory array. If enabled,
the Flash BIU contains a two-entry prefetch buffer, each entry containing 256 bits of data, and an
associated controller that prefetches sequential lines of data from the flash array into the buffer. Prefetch
Flash bus
interface
unit
(FBIU)
Flash memory
Flash memory block
Flash core
Control and
registers
interface
(MI)
V
FLASH
V
SS
V
DD
V
PP
Slave
bus
System
bus
status