Nexus
MPC5566 Microcontroller Reference Manual, Rev. 2
25-2 Freescale Semiconductor
25.1.1 Block Diagram
Figure 25.1.2 shows a general block diagram of the NDI components.
Figure 25-1. NDI General Block Diagram
25.1.2 Features
The NDI module is compliant with the IEEE-ISTO 5001-2003 standard. The following features are
implemented:
• 15- or 23-bit full duplex pin interface for medium and high visibility throughput
— One of two modes selected by register configuration: full port mode (FPM) and reduced port
mode (RPM). FPM comprises 12 MDO pins, and RPM comprises 4 MDO pins.
— Auxiliary output port
– One MCKO (message clock out) pin
– Four or 12 MDO (message data out) pins
JCOMP
Program, data,
ownership,
watchpoint,
trace
R/W register,
halt, step,
continue
Data,
watchpoint,
trace
Buffer
Program, data,
ownership,
watchpoint,
trace
R/W register,
R/W data,
halt, step,
continue
Read/write
access
Buffer
NZ6C3
Nexus port controller
(NPC)
JTAG port controller
RDY TDI TCK TDO TMS EVTI
Auxiliary port
MSEO[0:1] MCKO MDO(4 or 12) EVTO
• • •
Buffer
On-chip
memory
and I/O
Off-chip
memory
and I/O
XBAR
MMU
cache
Engine
1
CDC
Engine
1
2
eTPU
e200z6
1
Some MPC5500 devices have one eTPU engine, others have two engines.
eDMAC
NDEDI
NXDM
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