System Integration Unit (SIU)
MPC5566 Microcontroller Reference Manual, Rev. 2
Freescale Semiconductor 6-63
Refer to Table 6-19 for bit field definitions. Table 6-76 lists the PA fields for
PCSB[5]_PCSC[0]_GPIO[110].
6.3.1.77 Pad Configuration Registers 111–112 (SIU_PCR111–SIU_PCR112)
The SIU_PCR111–SIU_PCR112 registers control the function, direction, and electrical attributes of
ETRIG[0:1]_GPIO[111:112].
Figure 6-78. ETRIG[0:1]_GPIO[111:112] Pad Configuration Register (SIU_PCR111–SIU_PCR112)
Refer to Table 6-19 for bit field definitions. Table 6-77 lists the PA fields for ETRIG[0:1]_GPIO[111:112].
6.3.1.78 Pad Configuration Register 113 (SIU_PCR113)
The SIU_PCR113 register controls the function, direction, and electrical attributes of
TCRCLKA_IRQ
[7]_GPIO[113].
Figure 6-79. TCRCLKA_IRQ[7]_GPIO[113] Pad Configuration Register (SIU_PCR113)
Table 6-76. PCR110 PA Field Definitions
PA Field Pin Function
0b00 GPIO[110]
0b01 PCSB[5]
0b10 PCSC[0]
0b11 PCSB[5]
Address: Base + (0x011E–0x0120) Access: R/W
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
R 0 0 0 0 0
PA OBE
1
1
When ETRIG[0:1] is configured, the OBE has no effect. When configured as GPDO, set the OBE bit to 1.
IBE
2
2
When the pad is configured as an output, set the IBE bit to 1 to show the pin state in the GPDI register.
Clear the IBE bit to 0 to reduce power consumption. When configured as GPDI, set the IBE bit to 1.
0 0
ODE HYS SRC WPE WPS
W
RESET: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1
Table 6-77. PCR111–PCR112 PA Field Definitions
PA Field Pin Function
0b0 GPIO[111:112]
0b1 ETRIG[0:1]
Address: Base + 0x0122 Access: R/W
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
R 0 0 0 0
PA OBE
1
1
When configured as TCRCLKA or IRQ[7], the OBE bit has no effect. When configured as GPDO, set the OBE bit to 1.
IBE
2
2
When the pad is configured as an output, set the IBE bit to 1 to show the pin state in the GPDI register.
Clear the IBE bit to 0 to reduce power consumption. When configured as GPDI, set the IBE bit to 1.
0 0
ODE HYS SRC WPE WPS
W
RESET: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1