System Integration Unit (SIU)
MPC5566 Microcontroller Reference Manual, Rev. 2
6-78 Freescale Semiconductor
6.3.1.99 Pad Configuration Registers 167–178 (SIU_PCR167–SIU_PCR178)
The SIU_PCR167–SIU_PCR178 registers control the function, direction, and electrical attributes of
ETPUB[20:31]_GPIO[167:178]. The inputs and outputs of ETPUB[20:31] are connected.
Figure 6-100. ETPUB[20:31]_GPIO[167:178]
Pad Configuration Register (SIU_PCR167–SIU_PCR178)
Refer to Table 6-19 for bit field definitions. Table 6-99 lists the PA fields for
ETPUB[20:31]_GPIO[167:178].
6.3.1.100 Pad Configuration Register 179–188 (SIU_PCR179–SIU_PCR188)
The SIU_PCR179–SIU_PCR188 registers control the function, direction, and electrical attributes of
EMIOS[0:9]_ETPUA[0:9]_GPIO[179:188]. The input and output functions of EMIOS[0:9] are
connected. Only the output channels of ETPUA[0:9] are connected.
Figure 6-101. EMIOS[0:9]_ETPUA[0:9]_GPIO[179:188]
Pad Configuration Register (SIU_PCR179–SIU_PCR188)
Address: Base + (0x018E–0x01A4) Access: R/W
0123456789101112131415
R 00000
PA OBE
1
1
The OBE bit must be set to one for ETPUB[20:31] or GPIO[167:178] when configured as outputs.
IBE
2
2
When the pad is configured as an output, set the IBE bit to 1 to show the pin state in the GPDI register. Clear the IBE bit to 0
to reduce power consumption. The IBE bit must be set to one for ETPUB[20:31] or GPIO[167:178] when configured as inputs.
00
ODE HYS SRC WPE WPS
W
RESET: 000000000000001U
3
3
The weak pullup/down value at reset for ETPUB[20:31] pins is determined by WKPCFG.
Table 6-99. PCR167–PCR178 PA Field Definitions
PA Field Pin Function
0b0 GPIO[167:178]
0b1 ETPUB[20:31]
Address: Base + (0x01A6–0x01B8) Access: R/W
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
R 0 0 0 0
PA OBE
1
1
The OBE bit must be set to 1 for EMIOS[0:9] or GPIO[179:188] when configured as output.
IBE
2
2
When the pad is configured as an output, set the IBE bit to 1 to show the pin state in the GPDI register. Clear the IBE bit to 0
to reduce power consumption. The IBE bit must be set to 1 for EMIOS[0:9] or GPIO[179:188] when configured as inputs.
0 0
ODE HYS SRC WPE WPS
W
RESET: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 U
3
3
The weak pullup/down selection at reset for the EMIOS[0:9] pins is determined by the WKPCFG pin.
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