NXP Semiconductors MPC5566 - Receive Descriptor Ring Start (ERDSR)

Fast Ethernet Controller (FEC)
MPC5566 Microcontroller Reference Manual, Rev. 2
Freescale Semiconductor 15-29
15.3.4.3.2 Receive Descriptor Ring Start (ERDSR)
The ERDSR is written by the application. It provides a pointer to the start of the circular receive buffer
descriptor queue in external memory. This pointer must be 32-bit aligned; however, it is recommended it
be made 128-bit aligned (evenly divisible by 16).
This register is not reset and must be initialized by the application prior to operation.
Address Base + 0x0150 Access: RO
0 123456789101112131415
R000000000000000 0
W
Reset000000000000000 0
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R0 0 0 0 0 0 R_FSTART 0 0
W
Reset000001010000000 0
Figure 15-24. FIFO Receive Start Register (FRSR)
Table 15-24. FRSR Field Descriptions
Field Descriptions
0–21 Reserved, read as 0 (except bit 21, which is read as 1).
22–29
R_FSTART
Address of first receive FIFO location. Acts as delimiter between receive and transmit FIFOs.
30–31 Reserved, read as 0.
Address Base + 0x0180 Access: R/W
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
R
R_DES_START
W
Reset U
1
UUUUUUUUUUUUUUU
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R
R_DES_START
00
W
Reset U U U U U U U U U U U U U U U U
1
“U” signifies a bit that is uninitialized.
Figure 15-25. Receive Descriptor Ring Start Register (ERDSR)