Enhanced Serial Communication Interface (eSCI)
MPC5566 Microcontroller Reference Manual, Rev. 2
21-24 Freescale Semiconductor
If the TE bit is cleared during a transmission, the TXD output becomes idle after completion of the
transmission in progress. Clearing and then setting the TE bit during a transmission queues an idle
character to be sent after the frame currently being transmitted.
NOTE
When queueing an idle character, return the TE bit to logic 1 before the stop
bit of the current frame shifts out through the TXD output. Setting the TE
bit after the stop bit shifts out through the TXD output causes data
previously written to the eSCI data register to be lost. Toggle the TE bit for
a queued idle character while the TDRE flag is set and immediately before
writing the next byte to the eSCI data register.
21.4.4.5 Fast Bit Error Detection in LIN Mode
Fast bit error detection has been designed to allow flagging of LIN bit errors while they occur, rather than
flagging them after a byte transmission has completed. To use this feature, it is assumed a physical
interface connects to the LIN bus as shown in Figure 21-14.
Figure 21-14. Fast Bit Error Detection on a LIN Bus
If fast bit error detection is enabled (FBR = 1), the eSCI compares the transmitted and the received data
stream when the transmitter is active (not idle). After a mismatch between the transmitted data and the
received data is detected the following actions are performed:
• The LIN frame is aborted (provided LDBG=0).
• The bit error flag BERR is set.
• If SBSTP is 0, the remainder of the byte is transmitted normally.
• If SBSTP is 1, the remaining bits in the byte after the error bit are transmitted as 1s (idle).
To adjust to different bus loads the sample point at which the incoming bit is compared to the one which
was transmitted can be selected with the BESM13 bit (refer to Figure 21-15). If set, the comparison is
performed at RT clock 13, otherwise at RT clock 9 (refer to Section 21.4.5.3, “Data Sampling.”).
Bus Clock
Compare
Bit Error
Receive Shift
Register
Transmit Shift
Register
Sample Point
LIN Bus
RxD Pin
TxD Pin
Synchronizer Stage
LIN Physical Interface
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