NXP Semiconductors MPC5566 - Etpu Coherent Dual-Parameter Controller Register (ETPU_CDCR)

Enhanced Time Processing Unit (eTPU)
MPC5566 Microcontroller Reference Manual, Rev. 2
18-20 Freescale Semiconductor
18.4.3.2 eTPU Coherent Dual-Parameter Controller Register (ETPU_CDCR)
ETPU_CDCR configures and controls dual-parameter coherent transfers. For more information, refer to
the eTPU Reference Manual.
25
VIS
SCM visibility. Determines SCM visibility to the slave bus interface and resets the MISC state (but SCMMISEN
keeps its value).
0 SCM is not visible to the slave bus. Accessing SCM address space issues a bus error.
1 SCM is visible to the slave bus. The MISC state is reset.
This bit is write protected when any of the engines are not in halt or stop states. When VIS=1, the ETPU_ECR
MDIS bits are write protected, and only 32-bit aligned SCM writes are supported. The value written to SCM is
unpredictable if other transfer sizes are used.
26 – 30 Reserved
31
GTBE
Global time base enable. Enables time bases in both engines, allowing them to be started synchronously. An
assertion of GTBE also starts the eMIOS time base
1
. This enables the eTPU time bases and the eMIOS time
base to all start synchronously.
1 time bases in both eTPU engines and eMIOS are enabled to run.
0 time bases in both engines are disabled to run.
Note: When GTBE is turned off with Angle Mode enabled, the EAC must be reinitialized before GTBE is turned
on again.
1
The eMIOS also has a GTBE bit. Assertion of either the eMIOS or eTPU GTBE bit starts time bases for the eMIOS and eTPU,
refer to the eTPU Reference Manual.
Address: Base + 0x0000_0004 Access: R/W
0123456789101112131415
R
STS CTBASE PBBASE
W
Reset0000000000000000
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R
PWID
TH
PA RM0 W R PA RM1
W
Reset0000000000000001
Figure 18-6. eTPU Coherent Dual-Parameter Controller Register (ETPU_CDCR)
Table 18-6. ETPU_MCR Field Descriptions (continued)
Field Description