Enhanced Time Processing Unit (eTPU)
MPC5566 Microcontroller Reference Manual, Rev. 2
Freescale Semiconductor 18-19
4
MGEA
Microcode global exception engine A. Indicates that a global exception was asserted by microcode executed on
the respective engine. The determination of the reason why the global exception was asserted is application
dependent: it can be coded in an SDM status parameter, for instance. This bit is cleared by writing 1 to GEC.
0 No microcode-requested global exception pending.
1 Global exception requested by microcode is pending.
5
MGEB
Microcode global exception engine B. Indicates that a global exception was asserted by microcode executed on
the respective engine. The determination of the reason why the global exception was asserted is application
dependent: it can be coded in an SDM status parameter, for instance. This bit is cleared by writing 1 to GEC.
0 No microcode requested global exception pending.
1 Global exception requested by microcode is pending.
6
ILFA
Illegal instruction flag eTPU A. Set by the microengine to indicate that an illegal instruction was decoded in engine
A. This bit is cleared by host writing 1 to GEC. For more information about illegal instructions, refer to Section 9.6
in the eTPU Reference Manual.
0 Illegal Instruction not detected.
1 Illegal Instruction detected by eTPU A.
7
ILFB
Illegal instruction flag eTPU B. Set by the microengine to indicate that an illegal instruction was decoded in engine
B. This bit is cleared by host writing 1 to GEC. For more details, refer to the eTPU Reference Manual.
0 Illegal Instruction not detected.
1 Illegal Instruction detected by eTPU B.
8–10 Reserved
11–15
SCMSIZE
[0:4]
SCM size. Holds the number of 2 KB SCM Blocks minus 1. This value is MCU-dependent.
16–20 Reserved
21
SCMMISF
SCM MISC Flag. Set by the SCM MISC (multiple input signature calculator) logic to indicate that the calculated
signature does not match the expected value, at the end of a MISC iteration. For more details, refer to the eTPU
Reference Manual for more details.
0 Signature mismatch not detected.
1 MISC has read entire SCM array and the expected signature in ETPU_MISCCMPR does not match the value
calculated.
This bit is cleared by writing 1 to GEC.
22
SCM
MISEN
SCM MISC enable. Used for enabling/disabling the operation of the MISC logic. SCMMISEN is readable and
writable at any time. The MISC logic only operates when this bit is set to 1. When the bit is reset the MISC address
counter is set to the initial SCM address. When enabled, the MISC continuously cycles through the SCM
addresses, reading each and calculating a CRC. To save power, the MISC can be disabled by clearing the
SCMMISEN bit. For more details, refer to the eTPU Reference Manual.
0 MISC operation disabled. The MISC logic is reset to its initial state.
1 MISC operation enabled. (Toggling to 1 clears the SCMMISF bit)
SCMMISEN is cleared automatically when MISC logic detects an error; that is, when SCMMISF transitions from
0 to 1, disabling the MISC operation.
23–24 Reserved
Table 18-6. ETPU_MCR Field Descriptions (continued)
Field Description
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