NXP Semiconductors MPC5566 - Pulse;Edge Accumulation Mode (PEA)

Enhanced Modular Input/Output Subsystem (eMIOS)
MPC5566 Microcontroller Reference Manual, Rev. 2
Freescale Semiconductor 17-37
Figure 17-24. Double-action Output Compare with FLAG Set on Both Matches
17.4.4.4.7 Pulse/Edge Accumulation Mode (PEA)
The following table lists the pulse/edge accumulation mode settings:
The PEA mode returns the time taken to detect a desired number of input events. MODE[6] bit selects
between continuous or single shot operation.
After writing to register A1, the internal counter is cleared on the first input event, ready to start counting
input events and the selected timebase is latched into register B2. On the match between the internal
counter and register A1, a counter bus capture is triggered to register A2 and B2. The data previously held
in register B2 is transferred to register B1 and the FLAG bit is set to indicate that an event has occurred.
The desired time interval can be determined by subtracting register B1 from A2. Registers
EMIOS_CADRn and EMIOS_CBDRn return the values in register A2 and B1, respectively.
To guarantee coherent access, reading EMIOS_CADRn disables transfers between B2 and B1. These
transfers are disabled until the next read of the EMIOS_CBDRn register. Reading the EMIOS_CBDRn
register re-enables transfers from B2 to B1, to take effect at the next transfer event, as described above.
1
Table 17-20. PEA Operating Mode
MODE[0:6] Unified Channel PEA Operating Mode
0b0001000 Pulse/edge accumulation (continuous)
0b0001001 Pulse/edge accumulation (single shot)
1. If B1 was not updated due to B2 to B1 transfer being disabled after reading register EMIOS_CADRn, further
EMIOS_CADRn and EMIOS_CBDRn reads do not return coherent data until a new bus capture is triggered to registers
A2 and B2. The capture event is indicated when the channel FLAG asserts. If enabled, the FLAG also generates an inter-
rupt.
Selected
counter bus
FLAG
set event
A1 match
0xxxxxxx 0x001000 0x001000 0x001000
Notes:
1
Writing EMIOS_CADRn writes to A1.
2
Writing EMIOS_CBDRn writes to B1.
MODE[6] = 1
B1 match B1 match
0xxxxxxx 0x001100 0x0011000x001100
A1 match
Update to
A1 and B1
Output
flip-flop
A1 value
1
B1 value
2
A2 value transferred to A1 according to OUn bit.
B2 value transferred to B1 according to OUn bit.
0x000500 0x001000 0x001100 0x001000 0x001100