NXP Semiconductors MPC5566 - Detailed Signal Description

Signal Description
MPC5566 Microcontroller Reference Manual, Rev. 2
2-18 Freescale Semiconductor
2.3 Detailed Signal Description
This section gives detailed descriptions of the device signals. Read Section 2.2.2, “Device Signals
Summary,” for the signal properties.
7
PLLCFG[2] is tied to ground in this device.
8
The EBI is specified and tested at 1.8–3.3 V.
9
Do not configure both the primary function in ADDR[8:11]_GPIO[4:7] and the secondary function in CS[0:3]_ADDR[8:11]_GPIO[0:3] pins to be the
address input. Only configure one set of pins for the address input.
10
When using the EBI functions, select the function in the SIU_PCR register, and then enable the EBI functions in the EBI registers for these pins.
Both the SIU and EBI configurations must match to operation correctly.
11
The function and state of this pin(s) after execution of the BAM program is determined by the BOOTCFG[0:1] pins. Read Table 16-8 for details on
the External Bus Interface (EBI) configuration after execution of the BAM program.
12
ADDR[6:7] are for master accesses to increase the memory space and are not used for slave accesses to the chip.
13
GPIO is selected in the SIU_PCR register. When configured for EBI operation, the pin function of write enable (WE) or byte enable (BE) is specified
in the EBI_BRn and EBI_CAL_BRn registers for each chip select region.
14
MCKO is only enabled if debug mode is enabled. Debug mode can be enabled before or after exiting system reset (RSTOUT negated).
15
MDO[0] is driven high following a power-on reset until the system clock achieves lock, at which time it is then negated. There is an internal pull up
on MDO[0].
16
The function of the MDO[11:4]_GPIO[82:75] pins is selected during a debug port reset by the EVTI pin or by selecting FPM in the NPC_PCR. When
functioning as MDO[4:11] the pad configuration specified by the SIU does not apply. Read Section 2.3.3.6, “Nexus Message Data Out / GPIO
MDO[11:4]_GPIO[82:75]” for more detail on MDO[4:11] pin operation.
17
The pull-up on TDO is only functional when not in JTAG mode, that is with JCOMP negated.
18
The function and state of the FlexCAN A and eSCI A pins after execution of the BAM program is determined by the BOOTCFG[0:1] pins. Read
Table 16-9 for details on the FlexCAN and eSCI pin configuration after execution of the BAM program.
19
For compatibility to the MPC5554, always power V
DDEH6
and V
DDEH10
from the same power supply (3–5.25 V). To allow one DSPI to operate at a
different operating voltage, connect V
DDEH6
and V
DDEH10
to separate power supplies, but this configuration is not compatible with the MPC5554.
20
All analog input channels are connected to both ADC blocks. The supply designation for this pin(s) specifies only the ESD rail used.
21
To use this analog function, the PA field of the corresponding SIU_PCR register should be set to 0b11.
22
To select this function the PA field of the corresponding SIU_PCR register should be set for GPIO.
23
If analog features are used, tie V
DDEH9
to V
DDA1
.
24
Because other balls already are named EMIOS[14:15], the balls for these signals are named GPIO[203:204].
25
The GPIO[205] pin is a protect for pin for configuring an external boot for a double data rate memory.
26
The GPIO[206:207] pins are protect for pins for double data rate memory data strobes.
27
GPIO[206:207] can be selected as the source for the eQADC trigger in the eQADC trigger input select register (SIU_ETISR).
28
The function after reset of the XTAL pin is determined by the value of the signal on the PLLCFG[1] pin. When bypass mode is chosen XTAL has
no function and must be grounded.
29
When the FMPLL is configured for external reference mode, the V
DDE5
supply affects the acceptable signal levels for the external reference. Refer
to Section 11.1.4.2, “External Reference Mode.”
30
The function after reset of the EXTAL_EXTCLK pin is determined by the value of the signal on the PLLCFG[1] pin. If the EXTCLK function is chosen,
the valid operating voltage for the pin is 1.62–3.60 V. If the EXTAL function is chosen, the valid operating voltage is 3.3 V.
31
V
RC33
is the 3.3 V input for the voltage regulator control.
32
The V
DDAn
and V
SSAn
power supply inputs are split into separate traces in the package substrate. Each trace is bonded to a separate pad location,
which provides isolation between the analog and digital sections within each ADC.
33
Can be tied to 5.0 V for both read operation and program/erase.
34
Tie the V
STBY
pin to V
SS
if the battery backed SRAM is not used.
35
Both V
DDE2
and V
DDE3
pins are labeled as V
DDE2
pins on the BGA maps. V
DDE3
can be connected internally to V
DDE2
.
36
The V
DDEH9
segment can be powered from 3.0–5.0 V for mux address or SSI functions, but must meet the V
DDA
specifications of 4.5–5.25 V for
analog input function.
37
All pins with pad type F are driven to a high state if their V
DDE
segment is powered before V
DD33
.
38
The pins are reserved for the clock and inverted clock outputs for DDR memory interface.