Enhanced Modular Input/Output Subsystem (eMIOS)
MPC5566 Microcontroller Reference Manual, Rev. 2
17-6 Freescale Semiconductor
17.2.1.1 Output Disable Input—eMIOS Output Disable Input Signals
Output disable inputs to both the eMIOS and the eTPU modules are connected to EMIOS_Flag_Outn
signals according to Table 17-3.
17.3 Memory Map/Register Definition
Addresses of unified channel (UC) registers are specified as offsets from the channel’s base address,
otherwise the eMIOS base address is used as reference.
The overall address map organization is shown in Table 17-4.
Table 17-3. eMIOS Output Disable Input Signals
eMIOS Channel
1
1
All other EMIOS_Flag_Outn output signals are not connected.
eMIOS Output Disable
Input Signal
2
2
Each of the four internal eMIOS output disable input signals can be
programmed to disable the output of any eMIOS channel if that channel has
selected output disable capability by the setting of its EMIOS_CCRn[ODIS] bit,
and by specifying the output disable input in its EMIOS_CCRn[ODISSL] field.
eTPU Output
Disable
Input Signal
3
3
ETPUx_ODIy input signals disable outputs for eTPU engine x, channels (y*8)
through (y*8+7). Refer to the ETPU chapter for more details.
EMIOS_Flag_Out8 Output disable input 3
ETPUA_ODI3
EMIOS_Flag_Out9 Output disable input 2 ETPUA_ODI2
EMIOS_Flag_Out10 Output disable input 1 ETPUA_ODI1
EMIOS_Flag_Out11 Output disable input 0 ETPUA_ODI0
EMIOS_Flag_Out20 — ETPUB_ODI0
EMIOS_Flag_Out21 — ETPUB_ODI1
EMIOS_Flag_Out22 — ETPUB_ODI2
EMIOS_Flag_Out23 — ETPUB_ODI3
Table 17-4. eMIOS Memory Map
Address Register Name Register Description Bits
Base (0xC3FA_0000) EMIOS_MCR Module configuration register 32
Base + 0x0004 EMIOS_GFR Global flag register 32
Base + 0x0008 EMIOS_OUDR Output update disable register 32
Base + 0x000C–0x001F — Reserved —
Base + 0x0020 UC0 Unified channel 0 registers 256
Base + 0x0040 UC1 Unified channel 1 registers 256
Base + 0x0060 UC2 Unified channel 2 registers 256
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