NXP Semiconductors MPC5566 - DMA Programming Errors

Enhanced Direct Memory Access (eDMA)
MPC5566 Microcontroller Reference Manual, Rev. 2
Freescale Semiconductor 9-41
Figure 9-27. Example of Multiple Loop Iterations
Figure 9-28 lists the memory array terms and how the TCD settings interrelate.
Figure 9-28. Memory Array Terms
9.4.2 DMA Programming Errors
The eDMA performs various tests on the transfer control descriptor to verify consistency in the descriptor
data. Most programming errors are reported on a per channel basis with the exception of two errors: group
priority error and channel priority error, or EDMA_ESR[GPE] and EDMA_ESR[CPE], respectively.
DMA Request
Minor Loop 3
Current Major Loop
Iteration Count
(CITER)
Example Memory Array
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DMA Request
Minor Loop 2
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DMA Request
Minor Loop 1
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Major Loop
xADDR:
(Starting Address)
xSIZE:
(Size of one data
Minor Loop
(NBYTES in Minor
Loop, often the same
value
as xSIZE)
Offset (xOFF): Number of bytes
added to current address
after each transfer
(Often the same value
as xSIZE)
•
Minor Loop
Each DMA Source (S) and
Destination (D) has its own:
• Address (xADDR)
• Size (xSIZE)
• Offset (xOFF)
xLAST: Number of bytes
added to current address
Peripheral queues typically have
size and offset equal
to NBYTES
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•
after Major Loop
(Typically used to
loop back)
transfer)
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Last Minor Loop
• Modulo (xMOD)
• Last Address Adjustment
(xLAST) where x = S or D
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