NXP Semiconductors MPC5566 - Pad Configuration Registers 52 (SIU_PCR52)

System Integration Unit (SIU)
MPC5566 Microcontroller Reference Manual, Rev. 2
Freescale Semiconductor 6-33
6.3.1.28 Pad Configuration Registers 52 (SIU_PCR52)
The SIU_PCR52 register controls function, direction, and electrical attributes of
DATA[24]_FEC_COL_GPIO[52].
Figure 6-29. DATA[24]_FEC_COL_GPIO[52] Pad Configuration Registers (SIU_PCR52)
Refer to Table 6-19 for bit field definitions. Table 6-29 lists the PA fields for
DATA[24]_FEC_COL_GPIO[52].
6.3.1.29 Pad Configuration Registers 53 (SIU_PCR53)
The SIU_PCR53 register controls the function, direction, and electrical attributes of
DATA[25]_FEC_RX_DV_GPIO[53].
Figure 6-30. DATA[25]_FEC_RX_DV_GPIO[53] Pad Configuration Registers (SIU_PCR53)
Address: Base + 0x00A8 Access: R/W
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
R 0 0 0 0
PA OBE
1
1
When configured as DATA[24] or FEC_COL, the OBE bit has no effect.
When configured as GPDO, set the OBE bit to 1.
IBE
2
2
When the pad is configured as an output, set the IBE bit to 1 to put the pin state in the GPDI register.
Clear the IBE bit to 0 to reduce power consumption. When configured as GPDI, set the IBE bit to 1.
DSC ODE
3
3
When configured as DATA[24] or FEC_COL, clear the ODE bit to 0.
HYS
4
4
If external master operation is enabled, clear the HYS bit to 0.
0 0
WPE
5
5
Refer to the EBI section for weak pullup settings when configured as DATA[24] or FEC_COL.
WPS
5
W
RESET: 0 0 0 0 0 0 0 0 1 1 0 0 0 0 1 1
Table 6-29. PCR52 PA Field Descriptions
PA Field Pin Function
0b00 GPIO[52]
0b01 DATA[24]
0b10 FEC_COL
0b11 DATA[24]
Address: Base + 0x00AA Access: R/W
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
R 0 0 0 0
PA OBE
1
1
When configured as DATA[25] or FEC_RX_DV, the OBE bit has no effect.
When configured as GPDO, set the OBE bit to 1.
IBE
2
2
When the pad is configured as an output, set the IBE bit to 1 to show the pin state in the corresponding GPDI register.
Clear the IBE bit to 0 to reduce power consumption. When configured as GPDI, set the IBE bit to 1.
DSC ODE
3
3
When configured as DATA[25] or FEC_RX_DV, clear the ODE bit to 0.
HYS
4
4
If external master operation is enabled, clear the HYS bit to 0.
0 0
WPE
5
5
Refer to the EBI section for weak pullup settings when configured as DATA[25] or FEC_RX_DV.
WPS
5
W
RESET: 0 0 0 0 0 0 0 0 1 1 0 0 0 0 1 1