Enhanced Queued Analog-to-Digital Converter (eQADC)
MPC5566 Microcontroller Reference Manual, Rev. 2
19-82 Freescale Semiconductor
Figure 19-45. Non-coherency Detection When Transfers From a Command Sequence Are Interrupted
19.4.4 Result FIFOs
19.4.4.1 RFIFO Basic Functionality
There are six RFIFOs located in the eQADC. Each RFIFO is four entries deep, and each RFIFO entry is
16 bits long. Each RFIFO serves as a temporary storage location for the one of the result queues allocated
in system memory. All result data is saved in the RFIFOs before being moved into the system result
queues. When an RFIFO is not empty, the eQADC sets the corresponding EQADC_FISRn[RFDF] (see
Section 19.3.2.8, “eQADC FIFO and Interrupt Status Registers 0–5 (EQADC_FISRn)”). If
EQADC_IDCRn[RFDE] is asserted (see Section 19.3.2.7), the eQADC generates a request so that the
RFIFO entry is moved to a result queue. An interrupt request, served by the host CPU, is generated when
EQADC_IDCRn[RFDS] is negated, and an eDMA request, served by the eDMA, is generated when
RFDS is asserted. The host CPU or the eDMA responds to these requests by reading EQADC_RFPRn (see
Section 19.3.2.5, “eQADC Result FIFO Pop Registers 0–5 (EQADC_RFPRn)”) to retrieve data from the
RFIFO.
NOTE
Reading a word, halfword, or any bytes from EQADC_RFPRn pops an
entry from RFIFOn, and the RFCTRn field decrements by 1.
Configure the eDMA controller to read a single result (16-bit data) from the
RFIFO pop registers for every asserted eDMA request it acknowledges.
Refer to Section 19.5.2, “eQADC/eDMA Controller Interface” for eDMA
controller configuration guidelines.
Figure 19-46 describes the important components in the RFIFO. Each RFIFO is implemented as a circular
set of registers to avoid the need to move all entries at each push/pop operation. The pop next data pointer
always points to the next RFIFO message to be retrieved from the RFIFO when reading eQADC_RFPR.
The receive next data pointer points to the next available RFIFO location for storing the next incoming
Command sequence became non-coherent before command 4
was transferred. After command transfers resume, eQADC checks
for coherency only after command 4.
CF5_CB1_CM6
7
CF5_CB1_CM56
CF5_CB1_CM45
CF5_CB1_CM34
CF5_CB1_CM2
3
CF5_CB1_CM12
CF5_CB1_CM01
CF5_CB1_CM13
14
CF5_CB1_CM1213
CF5_CB1_CM1112
CF5_CB1_CM1011
CF5_CB1_CM9
10
CF5_CB1_CM89
CF5_CB1_CM78
Command sequence became non-coherent before command 11
was transferred. After command transfers resume, eQADC checks
for coherency only after command 11.
To Next Page
Loading...
