External Bus Interface (EBI)
MPC5566 Microcontroller Reference Manual, Rev. 2
Freescale Semiconductor 12-43
When using TBDIP = 1, the BDIP behavior changes to toggle between every beat when BSCY is a
non-zero value. Figure 12-26 shows an example of the TBDIP = 1 timing for the same four-beat burst
shown in Figure 12-25.
Figure 12-26. Burst 32-bit Read Cycle, One Wait State between Beats, TBDIP = 1
12.4.2.6 Small Accesses (Small Port Size and Short Burst Length)
In this context, a small access refers to an access whose burst length and port size are such that the number
of bytes requested by the internal master cannot all be fetched (or written) in one external transaction. This
is the case when the base register’s burst length bit (EBI_BRn[BL]) and port size bit (EBI_BRn[PS]) are
set such that one of two situations occur:
• Burst accesses are inhibited and the number of bytes requested by the master is greater than the
port size (16 or 32 bit) can accommodate in a single access.
• Burst accesses are enabled and the number of bytes requested by the master is greater than the
selected burst length (four words or eight words).
If this is the case, the EBI initiates multiple transactions until all the requested data is transferred. All the
transactions initiated to complete the data transfer are considered as an atomic transaction, so the EBI does
not allow other unrelated master accesses to intervene between the transfers. In external master mode, this
means that the EBI keeps BB
asserted and does not grant the bus to another master until the atomic
transaction is complete.
DATA is valid
Wait state
Wait state
CLKOUT
ADDR[8:31]
BDIP
DATA[0:31]
TA
RD_WR
TSIZ[0:1]
TS
OE
CS
[n]
Expects more data
ADDR[29:31] = ‘000’
‘00’
Wait state Wait state
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