External Bus Interface (EBI)
MPC5566 Microcontroller Reference Manual, Rev. 2
12-44 Freescale Semiconductor
Table 12-17 shows all the combinations of burst length, port size, and requested byte count that cause the
EBI to run multiple external transactions to fulfill the request.
In most cases, the timing for small accesses is the same as for normal single-beat and burst accesses, except
that multiple back-to-back external transfers are executed for each internal request. These transfers have
no additional dead cycles in-between that are not present for back-to-back stand-alone transfers except for
the case of writes with an internal request size greater than 64 bits, discussed in Section 12.4.2.6.2, “Small
Access Example #2: 32-byte Write with External TA.”
The following sections show a few examples of small accesses. The timing for the remaining cases in
Table 12-17 can be extrapolated from these and the other timing diagrams in this document.
Table 12-17. Small Access Cases
Byte Count
Requested by Internal
Master
Burst Length Port Size
Number of External
Accesses to Fulfill
Request
Non-burstable Chip-Select Banks (BI = 1) or Non-Chip-Select Access
4 1 beat 16-bit 2 or 1
1
1
In 32-bit data bus mode (DBM = 0 in EBI_MCR), two accesses are performed. In 16-bit data
bus mode (DBM = 1), one 2-beat burst access is performed and this is not considered a small
access case. See Section 12.4.2.11, “Non-Chip-Select Burst in 16-bit Data Bus Mode” for this
special DBM = 1 case.
8 1 beat 32-bit 2
8 1 beat 16-bit 4
32 1 beat 32-bit 8
32 1 beat 16-bit 16
Burstable Chip-Select Banks (BI = 0)
32 4 words 16-bit (8 beats)
32-bit (4 beats)
2
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