NXP Semiconductors MPC5566 - Pad Configuration Register 194 (SIU_PCR194)

System Integration Unit (SIU)
MPC5566 Microcontroller Reference Manual, Rev. 2
6-82 Freescale Semiconductor
6.3.1.105 Pad Configuration Register 194 (SIU_PCR194)
The SIU_PCR194 register controls the function, direction, and electrical attributes of
EMIOS[15]_IRQ[1]_CNRXD_GPIO[194]. Both input and output functions of EMIOS[15] are connected.
Figure 6-106. EMIOS[15]_IRQ[1]_CNRXD_GPIO[194] Pad Configuration Register (SIU_PCR194)
Refer to Table 6-19 for bit field definitions. Table 6-105 lists the PA fields for
EMIOS[15]_IRQ[1]_CNRXD_GPIO[194].
6.3.1.106 Pad Configuration Register 195 (SIU_PCR195)
The SIU_PCR195 register controls the function, direction, and electrical attributes of
EMIOS[16]_ETPUB[0]_GPIO[195]. Both the input and output functions of EMIOS[16] are connected.
Only the output channel of ETPUB[0] is connected.
Figure 6-107. EMIOS[16]_ETPUB[0]_GPIO[195] Pad Configuration Register (SIU_PCR195)
Address: Base + 0x01C4 Access: R/W
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
R 0 0 0
PA OBE
1
1
The OBE bit must be set to 1 for GPIO[194] when configured as output.
IBE
2
2
When the pad is configured as an output, set the IBE bit to 1 to show the pin state in the GPDI register. Clear the IBE bit to 0 to
reduce power consumption. The IBE bit must be set to 1 for CNRXD or GPIO[194] when configured as input.
0 0
ODE HYS SRC WPE WPS
W
RESET: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 U
3
3
The weak pullup/down selection at reset for the EMIOS[15] pin is determined by the WKPCFG pin.
Table 6-105. PCR194 PA Field Definitions
PA Field Pin Function
0b000 GPIO[194]
0b001 EMIOS[15]
0b010 IRQ[1]
0b011 EMIOS[15]
0b100 CNRXD
Address: Base + 0x01C6 Access: R/W
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
R 0 0 0 0
PA OBE
1
1
The OBE bit must be set to 1 for EMIOS[16] or GPIO[195] when configured as output.
IBE
2
2
When the pad is configured as an output, set the IBE bit to 1 to show the pin state in the GPDI register. Clear the IBE bit to 0
to reduce power consumption. The IBE bit must be set to 1 for EMIOS[16] or GPIO[195] when configured as input.
0 0
ODE HYS SRC WPE WPS
W
RESET: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 U
3
3
The weak pullup/down selection at reset for the EMIOS[16] pin is determined by the WKPCFG pin.