NXP Semiconductors MPC5566 - External Signal Description

Frequency Modulated Phase Locked Loop and System Clocks (FMPLL)
MPC5566 Microcontroller Reference Manual, Rev. 2
11-12 Freescale Semiconductor
11.2 External Signal Description
Table 11-2 lists external signals used by the FMPLL during normal operation.
11.3 Memory Map/Register Definition
Table 11-3 shows the FMPLL memory map locations.
11.3.1 Register Descriptions
The clock operation is controlled by the synthesizer control register (FMPLL_SYNCR) and status is
reported in the synthesizer status register (FMPLL_SYNSR). The following sections describe these
registers in detail.
11.3.1.1 Synthesizer Control Register (FMPLL_SYNCR)
The synthesizer control register (FMPLL_SYNCR) contains bits for defining the clock operation for the
system.
NOTE
To ensure proper operation for all MPC5500s, execute an mbar or msync
instruction between: the write to change the FMPLL_SYNCR[MFD], and
the read to check the lock status shown by FMPLL_SYNSR[LOCK].
Buffered writes to the FMPLL, as controlled by
PBRIDGE_A_OPACR[BW0], must be disabled.
Table 11-2. PLL External Pin Interface
Name I/O Type Function Pull
PLLCFG[0]_GPIO[208] I/O Configures the mode during reset. GPIO used otherwise. Up
PLLCFG[1]_GPIO[209] I/O Configures the mode during reset. GPIO used otherwise. Up
PLLCFG[2]
1
1
In this device, PLLCFG[2] is tied to ground.
I Configures the crystal oscillator range —
XTAL Output Output drive for external crystal —
EXTAL_EXTCLK Input Crystal external clock input —
V
DDSYN
Power Analog power supply (3.3 V ±10%) —
V
SSSYN
Ground Analog ground —
Table 11-3. FMPLL Module Memory Map
Address Register Name Register Description Bits
Base (0xC3F8_0000) FMPLL_SYNCR Synthesizer control register 32
Base + 0x0004 FMPLL_SYNSR Synthesizer status register 32
Base + 0x0008–0xC3F8_3FFF — Reserved —