NXP Semiconductors MPC5566 - External References

e200z6 Core Complex
MPC5566 Microcontroller Reference Manual, Rev. 2
3-34 Freescale Semiconductor
accumulator is partially visible to the programmer in that its results do not have to be explicitly read to use
them. Instead, they are always copied into a 64-bit destination GPR specified as part of the instruction. The
accumulator however, has to be explicitly cleared when starting a new MAC loop. Based on the type of
instruction, the accumulator can hold either a single 64-bit value or a vector of two 32-bit elements.
3.4 External References
In addition to the Power Architecture instructions, the device supports e200z6 core-specific instructions
and SPE APU instructions and VLE instructions. For further information see the following documents:
• e200z6 PowerPC
TM
Core Reference Manual
•PowerPC
TM
Microprocessor Family: The Programming Environment for 32-bit Microprocessors
• Book E: Enhanced PowerPC
TM
Architecture
• EREF: A Programmer's Reference Manual for Freescale Book E Processors
• VLEPIM: Variable Length Encoding (VLE) Extension Programming Interface Manual
• Addendum to e200z6 PowerPC
TM
Core Reference Manual: e200z6 with VLE
• Errata to e200z6 PowerPC
TM
Core Reference Manual, Rev. 0
3.5 Power Architecture Instruction Extensions – VLE
The variable length encoding (VLE) provides an extension to 32-bit Power Architecture. There are
additional operations defined using an alternate instruction encoding to enable reduced code footprint.
This alternate encoding set is selected on an instruction page basis. A single page attribute bit selects
between standard Power Architecture instruction encodings and VLE instructions for that page of memory.
This page attribute is an extension to the Power Architecture page attributes. Pages can be freely
intermixed, allowing for a mixture of code using both types of encodings.
Instruction encodings in pages marked as using the VLE extension are either 16 or 32 bits long, and are
aligned on 16-bit boundaries. Therefore, all instruction pages marked as VLE are required to use
big-endian byte ordering.
This section describes the various extensions to the Power Architecture instructions that support the VLE
extension.
rfci, rfdi, rfi Not the mask bit 62 of CSRR0, DSRR0, or SRR0 respectively.
The destination address is [D,C]SRR0[32:62] || 0b0.
bclr, bclrl, bcctr, bcctrl Not the mask bit 62 of the LR or CTR respectively.
The destination address is [LR,CTR][32:62] || 0b0.