External Bus Interface (EBI)
MPC5566 Microcontroller Reference Manual, Rev. 2
Freescale Semiconductor 12-29
The termination phase is where the cycle is terminated by the assertion of either TA (normal termination)
or TEA (termination with error). Termination is discussed in detail in Section 12.4.2.9, “Termination
Signals Protocol.”
12.4.2.4 Single-Beat Transfer
The flow and timing diagrams in this section are for the EBI configured as single master mode. Therefore,
arbitration is not needed and is not shown in these diagrams. See Section 12.4.2.10, “Bus Operation in
External Master Mode,” to read how the flow and timing diagrams change for external master mode.
12.4.2.4.1 Single-Beat Read Flow
The handshakes for a single beat read cycle are illustrated in the following flow and timing diagrams.
Figure 12-9. Basic Flow Diagram of a Single-Beat Read Cycle
Ye s
No
Receives address
Asserts transfer start (TS)
drives address and attributes
Master (EBI)
Drives data
Asserts transfer
acknowledge (TA)
Asserts transfer
acknowledge (TA)
Receives data
Slave
CS access
?
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