Enhanced Queued Analog-to-Digital Converter (eQADC)
MPC5566 Microcontroller Reference Manual, Rev. 2
Freescale Semiconductor 19-35
19.3.2.15 eQADC RFIFO Registers (EQADC_RF[0–5]Rn)
EQADC_RF[0–5]Rn provide visibility of the contents of a RFIFO for debugging purposes. Each RFIFO
has four registers which are uniquely mapped to its four 16-bit entries. Refer to Section 19.4.4, “Result
FIFOs,” for more information on RFIFOs. These registers are read only. Data written to these registers is
ignored.
Address: RFIFO0: Base + 0x0300 (RF0R0)
Base + 0x0304 (RF0R1)
Base + 0x0308 (RF0R2)
Base+0x030C (RF0R3)
RFIFO1: Base + 0x0340 (RF1R0)
Base + 0x0344 (RF1R1)
Base + 0x0348 (RF1R2)
Base + 0x034C (RF1R3)
RFIFO2: Base + 0x0380 (RF2R0)
Base + 0x0384 (RF2R1)
Base + 0x0388 (RF2R2)
Base + 0x038C (RF2R3)
Access: RO
RFIFO3: Base + 0x03C0 (RF3R0)
Base + 0x03C4 (RF3R1)
Base + 0x03C8 (RF3R2)
Base + 0x03CC (RF3R3)
RFIFO4: Base + 0x0400 (RF4R0)
Base + 0x0404 (RF4R1)
Base + 0x0408 (RF4R2
Base + 0x040C (RF4R3)
RFIFO5: Base + 0x0440 (RF5R0)
Base + 0x0444 (RF5R1)
Base + 0x0448 (RF5R2)
Base + 0x044C (RF5R3)
0123456789101112131415
R0000000000000000
W
Reset0000000000000000
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R RFIFO[0–5]_DATAn
W
Reset0000000000000000
Figure 19-18. eQADC RFIFOn Registers (EQADC_RF[0–5]Rn)
Table 19-24. EQADC_RF[0–5]Rn Field Descriptions
Fielld Description
0–31
RFIFO[0–5]
_DATAn
[0:15]
RFIFO[0–5] data n. Returns the value stored within the entry of RFIFO[0–5]. Each RFIFO is composed of four
16-bit entries, with register 0 being mapped to the entry with the smallest memory mapped address.
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