Enhanced Queued Analog-to-Digital Converter (eQADC)
MPC5566 Microcontroller Reference Manual, Rev. 2
19-66 Freescale Semiconductor
19.4.3.3 External Trigger from eTPU or eMIOS Channels
The six eQADC external trigger inputs can be connected to either an external pin (either ETRIG0,
ETRIG1, GPIO206, or GPIO207), an eTPU channel, or an eMIOS channel. The input source for each
eQADC external trigger is individually specified in the eQADC trigger input select register (SIU_ETISR)
in the SIU block.
The eQADC trigger numbers specified by SIU_ETISR[TSEL(0–5)] correspond to CFIFO numbers 0–5.
To calculate the CFIFO number that each trigger is connected to, divide the eDMA channel number by 2.
A complete description of the eTPU and eMIOS trigger function and configuration is found in
Section 6.4.5.1, “eQADC External Trigger Input Multiplexing.”
19.4.3.4 External Trigger Event Detection
The digital filter length field in Section 19.3.2.3, “eQADC External Trigger Digital Filter Register
(EQADC_ETDFR),” specifies the minimum number of system clocks that the external trigger signals 0
and 1 must be held at a logic level to be recognized as valid. All ETRIG signals are filtered. A counter for
each queue trigger is implemented to detect a transition between logic levels. The counter counts at the
system clock rate. The corresponding counter is cleared and restarted each time the signal transitions
between logic levels. When the corresponding counter matches the value specified by the digital filter
length field in Section 19.3.2.3, “eQADC External Trigger Digital Filter Register (EQADC_ETDFR),” the
eQADC considers the ETRIG logic level to be valid and passes that new logic level to the rest of the
eQADC.
The filter is only for filtering the ETRIG signal. Logic after the filter checks for transitions between filtered
values, such as for detecting the transition from a filtered logic level zero to a filtered logic level one in
rising edge external trigger mode. The eQADC can detect rising edge, falling edge, or level gated external
triggers. The digital filter is always active independently of the status of the MODEn field in
Section 19.3.2.6, “eQADC CFIFO Control Registers 0–5 (EQADC_CFCRn),” but the edge, level
detection logic is only active when MODEn is set to a value different from disabled, and in case MODEn
is set to single scan mode, when the SSS bit is asserted. Note that the time necessary for a external trigger
event to result into a CFIFO status change is not solely determined by the DFL field in the Section 19.3.2.3,
“eQADC External Trigger Digital Filter Register (EQADC_ETDFR).” After being synchronized to the
system clock and filtered, a trigger event is checked against the CFIFO trigger mode. Only then, after a
valid trigger event is detected, the eQADC accordingly changes the CFIFO status. Refer to Figure 19-38
for an example.
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