Deserial Serial Peripheral Interface (DSPI)
MPC5566 Microcontroller Reference Manual, Rev. 2
20-50 Freescale Semiconductor
20.4.4.7.3 Serial Chaining
Serial chaining allows transfers of DSI frames consisting of concatenated bits from multiple DSPIs. The
concatenated frames can be from 8- to 64-bits long. Figure 20-28 shows an example of how the modules
can be connected.
Figure 20-28. Example of Serial Chaining of DSPI A, B, C and D
In the MCU (master), the SOUT of DSPI A is connected to the SIN of DSPI B (slave). The SOUT of the
DSPI B (slave) is connected to the SIN input of the DSPI C and so on (slave). The SOUT of the last on-chip
DSPI slave is connected to the SIN of the external SPI slave. The SOUT of the external SPI slave is
connected to the SIN of DSPI_A master.
The DSPI A master controls and initiates all transfers, but the slave DSPIs use the trigger output signal
MTRIG
to indicate to the DSPI_A master that a trigger condition has occurred. When an on-chip DSPI
slave has a change in data to be serialized it can assert the MTRIG
signal to the DSPI master which initiates
the transfer. When a DSPI slave has its ht signal asserted, its MTRIG
signal asserts and propagates trigger
signals from other DSPI slaves to the DSPI master.
The MTOCNT field in the DSPIx_DSICR must be written with the total number of bits to be transferred.
The MTOCNT field must equal the sum of all FMSZ fields in the selected DSPIx_CTARs for the DSPI
master and all DSPI slaves. For example if one 16-bit DSI frame is created by concatenating 8 bits from
the DSPI master, and 4 bits from each of the DSPI slaves in Figure 20-28, the DSPI master’s frame size
must be set to eight in the FMSZ field, and the DSPI slaves’ frame size must be set to four. The largest DSI
frame supported by the MTOCNT field is64 bits. Any number of DSPIs can be connected together to
concatenate DSI frames, as long as each DSPI transfers a minimum of 4 bits and a maximum of 16 bits
and the total size of the concatenated frame is less than or equal to64 bits long.
SOUT
ht
SCK
SIN
MTRIG
SS
DSPI A
SOUT
ht
SCK
SIN
PCS[0]
SINA
PCSA[0]
SCKA
(master)
DSPI B
(slave)
SOUT
SCK
SIN
MTRIG
SS
DSPI C
(slave)
SOUTC
SCKSS
SIN
Slave device
SPI
SOUT
MCU
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