NXP Semiconductors MPC5566 - External (or Central) Bus Arbiter

External Bus Interface (EBI)
MPC5566 Microcontroller Reference Manual, Rev. 2
Freescale Semiconductor 12-51
Figure 12-32. Bus Arbitration Flow Chart
12.4.2.8.1 External (or Central) Bus Arbiter
The external arbiter can be either another MCU in a two master system, or a separate central arbiter device.
When an MCU is configured to use external arbitration, that MCU asserts BR when it needs ownership of
the external bus, and it waits for BG to be asserted from the external arbiter. For timing reasons, a latched
(one cycle delayed) version of BG is used by the EBI in external arbitration mode. This is not a
requirement of the protocol. After BG assertion is received and BB is sampled negated for two cycles, the
MCU asserts BB and initiates the transaction. An MCU operating under external arbitration run
back-to-back accesses without rearbitration as long as it is still receiving BG asserted. If BG is negated
during a transaction, the MCU must rearbitrate for the bus before the next transaction. The determination
of priority between masters is determined entirely by the external arbiter in this mode.
Figure 12-33 shows example timing for the case of two masters connected to a central arbiter. In this case,
the BR
0 and BR 1 signals shown are inputs to the arbiter from the BR pin of each master. The BG 0 and
BG
1 signals are outputs from the arbiter that connect to the BG pin of each master.
1. Wait for BB to negate for 2 cycles.
2. Assert BB to become next master.
3. Negate BR (can choose to keep it
asserted if another request is pending).
Acknowledge bus mastership
Assert BR.
Request the bus
Perform data transfer.
Operate as bus master
Negate BB.
Release bus mastership
Negate BG (can choose to keep it
Terminate arbitration
Assert BG.
Grant bus arbitration
asserted to park bus master).
Requesting Device
Arbiter