NXP Semiconductors MPC5566 - Emios Channel a Data Register (Emios_Cadrn)

Enhanced Modular Input/Output Subsystem (eMIOS)
MPC5566 Microcontroller Reference Manual, Rev. 2
Freescale Semiconductor 17-11
17.3.1.4 eMIOS Channel A Data Register (EMIOS_CADRn)
Depending on the mode of operation, internal registers A1 or A2, used for matches and captures, can be
assigned to address EMIOS_CADRn. Both A1 and A2 are cleared by reset. Table 17-8 summarizes the
EMIOS_CADRn writing and reading accesses for all operating modes.
Refer to Section 17.4.4.4, “Unified Channel Operating Modes” for more information.
17.3.1.5 eMIOS Channel B Data Register (EMIOS_CBDRn)
Depending on the mode of operation, internal registers B1 or B2 can be assigned to address
EMIOS_CBDRn. Both B1 and B2 are cleared by reset. Table 17-8 summarizes the EMIOS_CBDRn
writing and reading accesses for all operating modes.
Refer to Section 17.4.4.4, “Unified Channel Operating Modes” for more information.
NOTE
The EMIOS_CBDRn must not be read speculatively. For future
compatibility, the TLB entry covering the EMIOS_CBDRn must be
configured to be guarded.
Address: UCn Base + 0x0000 Access: R/W
0123456789101112131415
R00000000
A
W
Reset0000000000000000
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R
A
W
Reset0000000000000000
Figure 17-5. eMIOS Channel A Data Register (EMIOS_CADRn)
Address: UCn Base + 0x0004 Access: R/W
0123456789101112131415
R00000000
B
W
Reset0000000000000000
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R
B
W
Reset0000000000000000
Figure 17-6. eMIOS Channel B Data Register (EMIOS_CBDRn)