Nexus
MPC5566 Microcontroller Reference Manual, Rev. 2
Freescale Semiconductor 25-75
25.17.1 NXDM Nexus Register Map
25.17.2 NXDM Registers
Detailed register definitions for the NXDM implementation are as follows:
Table 25-46. NXDM Register Map
Nexus Register
Nexus Access
Opcode
Read/Write
Read
Address
Write
Address
Client Select Control (CSC)
1
1
The CSC and PCR registers are shown in this table as part of the Nexus programmer’s model. They are only present
at the top level Nexus3 controller (NPC), not in the NXDM module. The device’s CSC register is readable through
Nexus3; the PCR is shown for reference only.
0x1 R 0x02 –
Port Configuration Register (PCR)
1
Refer to NPC R/W – –
Development Control 1 (DC1_n) 0x2 R/W 0x04 0x05
Development Control 2 (DC2_n) 0x3 R/W 0x05 0x06
Watchpoint Trigger (WT_n) 0xB R/W 0x16 0x17
Data Trace Control (DTC_n) 0xD R/W 0x1A 0x1B
Data Trace Start Address 1 (DTSA1_n) 0xE R/W 0x1C 0x1D
Data Trace Start Address 2 (DTSA2_n) 0xF R/W 0x1E 0x1F
Data Trace End Address 1 (DTEA1_n) 0x12 R/W 0x24 0x25
Data Trace End Address 2 (DTEA2_n) 0x13 R/W 0x26 0x27
Breakpoint/Watchpoint Control Register 1 (BWC1_n) 0x16 R/W 0x2C 0x2D
Breakpoint/Watchpoint Control Register 2 (BWC2_n) 0x17 R/W 0x2E 0x2F
Breakpoint/Watchpoint Address Register 1 (BWA1_n) 0x1E R/W 0x3C 0x3D
Breakpoint/Watchpoint Address Register 2 (BWA2_n) 0x1F R/W 0x3E 0x3F
Reserved 0x20–0x3F – 0x40–0x7E 0x41–0x7F
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