Deserial Serial Peripheral Interface (DSPI)
MPC5566 Microcontroller Reference Manual, Rev. 2
Freescale Semiconductor 20-37
State transitions from RUNNING to STOPPED occur on the next frame boundary if a transfer is in
progress, or on the next system clock cycle if no transfers are in progress.
20.4.3 Serial Peripheral Interface (SPI) Configuration
The SPI configuration transfers data serially using a shift register and a selection of programmable transfer
attributes. The DSPI is in SPI configuration when the DCONF field in the DSPIx_MCR is 0b00. The SPI
frames can be from 4 to 16 bits long. The data to be transmitted can come from queues stored in RAM
external to the DSPI. Host software or an eDMA controller can transfer the SPI data from the queues to a
first-in first-out (FIFO) buffer. The received data is stored in entries in the receive FIFO (RX FIFO) buffer.
Host software or an eDMA controller transfers the received data from the RX FIFO to memory external
to the DSPI.
The FIFO buffer operations are described in Section 20.4.3.4, “Using the TX FIFO Buffering
Mechanism,” and Section 20.4.3.5, “Using the RX FIFO Buffering Mechanism.”
The interrupt and DMA request conditions are described in Section 20.4.9, “Interrupts and DMA
Requests.”
The SPI configuration supports two module-specific modes; master mode and slave mode. The FIFO
operations are similar for the master mode and slave mode. The main difference is that in master mode the
DSPI initiates and controls the transfer according to the fields in the SPI command field of the TX FIFO
entry. In slave mode the DSPI only responds to transfers initiated by a bus master external to the DSPI and
the SPI command field of the TX FIFO entry is ignored.
20.4.3.1 SPI Master Mode
In SPI master mode the DSPI initiates the serial transfers by controlling the serial communications clock
(SCKx) and the peripheral chip select (PCSx) signals. The SPI command field in the executing TX FIFO
entry determines which CTARs are used to set the transfer attributes and which PCSx signal to assert. The
command field also contains various bits that help with queue management and transfer protocol. The data
field in the executing TX FIFO entry is loaded into the shift register and shifted out on the serial out
(SOUTx) pin. In SPI master mode, each SPI frame to be transmitted has a command associated with it
allowing for transfer attribute control on a frame by frame basis.
See Section 20.3.2.6, “DSPI PUSH TX FIFO Register (DSPIx_PUSHR),” for details on the SPI command
fields.
20.4.3.2 SPI Slave Mode
In SPI slave mode the DSPI responds to transfers initiated by an SPI bus master. The DSPI does not initiate
transfers. Certain transfer attributes such as clock polarity, clock phase and frame size must be set for
successful communication with an SPI master. The SPI slave mode transfer attributes are set in the
DSPIx_CTAR0.
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