MPC5566 Microcontroller Reference Manual, Rev. 2
Freescale Semiconductor 4-1
Chapter 4
Reset
4.1 Introduction
The following reset sources are supported in this MCU:
• Power-on reset
• External reset
• Loss-of-lock reset
• Loss-of-clock reset
• Watchdog timer/debug reset
• JTAG reset
• Checkstop reset
• Software system reset
• Software external reset
All reset sources are processed by the reset controller, which is located in the SIU module. The reset
controller monitors the reset input sources, and upon detection of a reset event, resets internal logic and
controls the assertion of the RSTOUT pin. The RSTOUT signal may be automatically asserted by writing
the SER bit in the SIU_SRCR to 1. The RSTOUT signal stays asserted for a number of system clocks
1
determined by the configuration of the PLL. This does not reset the MCU. All other reset sources initiate
an internal reset of the MCU.
Refer to Section 4.2.2, “Reset Output (RSTOUT)”.
For all reset sources, the BOOTCFG[0:1] and PLLCFG[0:1] signals can be used to determine the boot
mode and the configuration of the FMPLL, respectively. If the RSTCFG
pin is asserted during reset, the
values on the BOOTCFG[0:1] pins are latched in the SIU_RSR 4 clock cycles prior to the negation of the
RSTOUT
pin, determining the boot mode. The values on the PLLCFG[0:1] pins are latched at the negation
of the RSTOUT
pin, determining the configuration of the FMPLL. If the RSTCFG pin is negated during
reset, the FMPLL defaults to normal operation (PLL enabled) with a crystal reference and the boot mode
(latched in the SIU_RSR) is defaulted to internal boot from flash.
The reset status register (SIU_RSR) gives the source of the last reset and indicates whether a glitch has
occurred on the RESET pin. The SIU_RSR is updated for all reset sources except the JTAG reset.
All reset sources initiate execution of the MCU boot assist module (BAM) program with the exception of
the software external reset.
1. Unless noted otherwise, the use of ‘clock’ or ‘clocks’ in this section is a reference to the system clock.
To Next Page
Loading...
