Reset
MPC5566 Microcontroller Reference Manual, Rev. 2
4-2 Freescale Semiconductor
The reset configuration halfword (RCHW) provides several basic functions at reset. It provides a means
to locate the boot code, determines if flash memory is programmed or erased, enables or disables the
watchdog timer, configures the MMU to boot as either classic Power Architecture Book E code or as
Freescale VLE code, and if booting externally, sets the bus size. The location of the RCHW is specified
by the state of the BOOTCFG[0:1] pins. These pins determine whether the RCHW is located in internal
flash, located in external memory, or whether a serial or CAN boot is configured.
Refer to Section Chapter 2, “Signal Description” for a complete description of the BOOTCFG[0:1] pins.
The BAM program reads the values of the BOOTCFG[0:1] pins from the BOOTCFG field of the
SIU_RSR, then reads the RCHW from the specified location and uses the RCHW value to determine and
execute the specified boot procedure.
Refer to Section 4.4.3, “Reset Configuration and Configuration Pins,” for a complete description.
4.2 External Signal Description
4.2.1 Reset Input (RESET)
The RESET pin is an active low input that is asserted by an external device during a power-on or external
reset. The internal reset signal asserts only if the RESET pin is asserted for 10 clock cycles. Assertion of
the RESET pin while the device is in reset causes the reset cycle to start over. The RESET pin also has an
associated glitch detector which detects spikes greater than two clocks in duration that fall below the
switch point of the input buffer logic.
Refer to Section 6.4.2.1, “RESET Pin Glitch Detect.”
4.2.2 Reset Output (RSTOUT)
The RSTOUT pin is an active low output that uses a push/pull configuration. The RSTOUT pin is driven
to the low state by the MCU for all internal and external reset sources.
After the negation of the RESET input, if the PLL is configured for 1:1 (dual controller) mode or bypass
mode, the RSTOUT
signal is asserted for 16000 clocks, plus four clocks for sampling of the configuration
pins. If the PLL is configured for any other operating mode, the RSTOUT
signal is asserted for 2400
clocks, plus four clocks for sampling of the configuration pins. The RSTOUT
pin is asserted by a write to
the SER bit of the system reset control register (SIU_SRCR).
Refer to Section 11.1.4, “FMPLL Modes of Operation” for details of PLL configuration.
NOTE
During a power on reset, RSTOUT
is tri-stated.
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