NXP Semiconductors MPC5566 - Eqadc Trigger Input Select Register (SIU_ETISR)

System Integration Unit (SIU)
MPC5566 Microcontroller Reference Manual, Rev. 2
6-108 Freescale Semiconductor
Table 6-148 describes the PDIn bit field in the general purpose data input registers:
6.3.1.161 eQADC Trigger Input Select Register (SIU_ETISR)
The SIU_ETISR defines the input sources for the eQADC trigger. The eQADC triggers numbered 0–5 are
defined in TSEL 0–5 and correspond to CFIFOs 0–5. To determine the valid input pins a trigger activates,
divide the DMA channel number by two, and consult Table 6-149. For example, DMA channel 2 is
connected to eQADC CFIFO 1, therefore TSEL[1] can be triggered by eTPUA[31], eMIOS[11] or
ETRIG[1]. To use a trigger, TSEL must be initialized.
When an eQADC trigger is connected, the timer output is connected to the eQADC CFIFO trigger input.
To trigger the eQADC, the timer output pin must change to the state that the eQADC recognizes as a
trigger. Rising or falling edges, and low- or high-gated triggers are all valid events that activate a trigger,
therefore, it is possible to activate the eQADC trigger immediately if desired.
The following table lists the interconnections for the eQADC triggers:
Table 6-148. SIU_GPDIn Field Descriptions
Name Description
PDIn Pin data in. This bit reflects the input state on the external GPIO pin for the register.
If PCRn[IBE] = 1, then:
0 Signal on pin is less than or equal to V
IL
.
1 Signal on pin is greater than or equal to V
IH
.
Table 6-149. Trigger Interconnections
TSEL Field
(Trigger
Number)
eQADC
CFIFO
eQADC DMA
Channel
eTPUA
Channel
eMIOS
Channel
ETRIG
Input
GPIO[206]:
GPIO[207]
0 0 0 eTPUA[30] eMIOS[10] ETRIG[0] GPIO[206]
1 1 2 eTPUA[31] eMIOS[11] ETRIG[1] GPIO[207]
2 2 4 eTPUA[29] eMIOS[15] ETRIG[0] GPIO[206]
3 3 6 eTPUA[28] eMIOS[14] ETRIG[1] GPIO[207]
4 4 8 eTPUA[27] eMIOS[13] ETRIG[0] GPIO[206]
5 5 10 eTPUA[26] eMIOS[12] ETRIG[1] GPIO[207]