NXP Semiconductors MPC5566 - Port Size Configuration Per Chip Select (16 or 32 Bits)

External Bus Interface (EBI)
MPC5566 Microcontroller Reference Manual, Rev. 2
12-24 Freescale Semiconductor
12.4.1.8 Port Size Configuration per Chip Select (16 or 32 Bits)
The EBI supports memories with data widths of 16 or 32 bits. The port size (PS) for a chip select is
configured using the PS bit in the base register.
12.4.1.9 Port Size Configuration per Calibration Chip Select (16 Bits)
The port size for calibration must be 16 bits wide.
12.4.1.10 Configurable Wait States
From zero to 15 wait states can be programmed for any cycle that the memory controller generates, via the
SCY bits in the appropriate option register. From zero to three wait states between burst beats can be
programmed using the BSCY bits in the appropriate option register.
12.4.1.11 Four Chip Select (CS[0:3]) Signals
The EBI contains four chip select signals, controlling four independent memory banks. See
Section 12.4.1.5, “Memory Controller with Support for Various Memory Types,” for more details on chip
select bank configuration.
12.4.1.12 Support for Dynamic Calibration with Up to Four Chip Selects
The EBI contains four calibration chip select signals, controlling four independent memory banks on an
optional second external bus for calibration. See Section 12.4.2.12, “Calibration Bus Operation” for more
details on using the calibration bus.
12.4.1.13 Four Write/Byte Enable (WE/BE) Signals — 416 BGA Package and
VertiCal Assembly
The functionality of the WE/BE[0:3] signals depends on the value of the WEBS bit in the base register.
Setting WEBS to 1 configures these pins as BE[0:3], while clearing them to 0 configures them as WE[0:3].
WE[0:3] signals are asserted only during write accesses, while BE[0:3] signals are asserted for both read
and write accesses. The timing of the WE
/BE[0:3] signals remains the same in either case.
The upper write/byte enable (WE/BE[0]) indicates that the upper eight bits of the data bus (DATA[0:7])
contain valid data during a write/read cycle. The upper middle write/byte enable (WE/BE[1]) indicates that
the upper middle eight bits of the data bus (DATA[8:15]) contain valid data during a write/read cycle. The
lower middle write/byte enable (WE/BE[2]) indicates that the lower middle eight bits of the data bus
(DATA[16:23]) contain valid data during a write/read cycle. The lower write/byte enable (WE/BE[3])
indicates that the lower eight bits of the data bus (DATA[24:31]) contain valid data during a write/read
cycle.
The write/byte enable lines affected in a transaction for a 32-bit port (PS = 0) and a 16-bit port (PS = 1)
are shown in Table 12-13. Only big endian byte ordering is supported by the EBI.