NXP Semiconductors MPC5566 - Pad Configuration Registers 51 (SIU_PCR51)

System Integration Unit (SIU)
MPC5566 Microcontroller Reference Manual, Rev. 2
6-32 Freescale Semiconductor
Refer to Table 6-19 for bit field definitions. Table 6-27 lists the PA fields for
DATA[22]_FEC_RXD[0]GPIO[50].
6.3.1.27 Pad Configuration Registers 51 (SIU_PCR51)
The SIU_PCR51 register controls the function, direction, and electrical attributes of
DATA[23]_FEC_TXD[3]_GPIO[51].
Figure 6-28. DATA[23]_FEC_TXD[3]_GPIO[51] Pad Configuration Registers (SIU_PCR51)
Refer to Table 6-19 for bit field definitions. Table 6-28 lists the PA fields for
DATA[23]_FEC_TXD[3]_GPIO[51].
Table 6-27. PCR50 PA Field Descriptions
PA Field Pin Function
0b00 GPIO[50]
0b01 DATA[22]
0b10 FEC_RXD[0]
0b11 DATA[22]
Address: Base + 0x00A6 Access: R/W
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
R 0 0 0 0
PA OBE
1
1
When configured as DATA[23] or FEC_TXD[3], the OBE bit has no effect.
When configured as GPDO, set the OBE bit to 1.
IBE
2
2
When the pad is configured as an output, set the IBE bit to 1 to show the pin state in the GPDI register.
Clear the IBE bit to 0 to reduce power consumption. When configured as GPDI, set the IBE bit to 1.
DSC ODE
3
3
When configured as DATA[23] or FEC_TXD[3], clear the ODE bit to 0.
HYS
4
4
If external master operation is enabled, clear the HYS bit to 0.
0 0
WPE
5
5
Refer to the EBI section for weak pullup settings when configured as DATA[23] or FEC_TXD[3].
WPS
5
W
RESET: 0 0 0 0 0 0 0 0 1 1 0 0 0 0 1 1
Table 6-28. PCR51 PA Field Descriptions
PA Field Pin Function
0b00 GPIO[51]
0b01 DATA[23]
0b10 FEC_TXD[3]
0b11 DATA[23]