IEEE 1149.1 Test Access Port Controller (JTAGC)
MPC5566 Microcontroller Reference Manual, Rev. 2
Freescale Semiconductor 24-11
24.5 Initialization/Application Information
The test logic is a static logic design, and TCK can be stopped in either a high or low state without loss of
data. However, the system clock is not synchronized to TCK internally. Any mixed operation using both
the test logic and the system functional logic requires external synchronization.
To initialize the JTAGC module and enable access to registers, the following sequence is required:
1. Set the JCOMP signal to logic 1, thereby enabling the JTAGC TAP controller.
2. Load the appropriate instruction for the test or action to be performed.
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