External Bus Interface (EBI)
MPC5566 Microcontroller Reference Manual, Rev. 2
12-28 Freescale Semiconductor
12.4.2.1 External Clocking
The CLKOUT signal sets the frequency of operation for the bus interface directly. Internally, the MCU
uses a phase-locked loop (PLL) circuit to generate a master clock for all of the MCU circuitry (including
the EBI) which is phase-locked to the CLKOUT signal. In general, all signals for the EBI are specified
with respect to the rising-edge of the CLKOUT signal, and they are guaranteed to be sampled as inputs or
changed as outputs with respect to that edge.
12.4.2.2 Reset
Upon detection of internal reset, the EBI immediately terminates all transactions.
12.4.2.3 Basic Transfer Protocol
The basic transfer protocol defines the sequence of actions that must occur on the external bus to perform
a complete bus transaction. A simplified scheme of the basic transfer protocol is shown in Figure 12-8.
Figure 12-8. Basic Transfer Protocol
The arbitration phase is where bus ownership is requested and granted. This phase is not needed in single
master mode because the EBI is the permanent bus owner in this mode. Arbitration is discussed in detail
in Section 12.4.2.8, “Arbitration.”
The address transfer phase specifies the address for the transaction and the transfer attributes that describe
the transaction. The signals related to the address transfer phase are TS, ADDR, CS[0:3], RD_WR,
TSIZ[0:1], and BDIP. The address and its related signals (with the exception of TS, BDIP) are driven on
the bus with the assertion of the TS signal, and kept valid until the bus master receives TA asserted
(the EBI holds them one cycle beyond TA for writes and external TA accesses). For writes with internal
TA
, RD_WR is not held one cycle past TA.
The data transfer phase performs the transfer of data, from master to slave (in write cycles) or from slave
to master (on read cycles), if any is to be transferred. The data phase transfer a single beat of data
(one to four bytes) for non-burst operations or a 2-beat (special EBI_MCR[DBM] = one case only), 4-beat,
8-beat, or 16-beat burst of data (two or four bytes per beat depending on port size) when burst is enabled.
On a write cycle, the master must not drive write data until after the address transfer phase is complete.
This avoids electrical contentions when switching between drivers. The master must start driving write
data one cycle after the address transfer cycle. The master can stop driving the data bus as soon as it
samples the TA
line asserted on the rising edge of CLKOUT. To facilitate asynchronous write support, the
EBI keeps driving valid write data on the data bus until one clock after the rising edge when RD_WR
(and WE
for chip select accesses) are negated. See Figure 12-14 for an example of write timing.
On a read cycle, the master accepts the data bus contents as valid on the rising edge of the CLKOUT in
which the TA
signal is sampled asserted. See Figure 12-10 for an example of read timing.
Arbitration Address transfer Data transfer Te r min ati on
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