System Integration Unit (SIU)
MPC5566 Microcontroller Reference Manual, Rev. 2
6-6 Freescale Semiconductor
The BOOTCFG values are used only if the RSTCFG asserts while RSTOUT is asserted. Otherwise, the
default value for BOOTCFG (0b00) in the reset status register (SIU_RSR) is used, as shown in Table 6-4.
6.2.1.5 I/O Weak Pullup Reset Configuration (WKPCFG)
The WKPCFG signal is applied when the internal reset signal asserts (indicated by RSTOUT asserting),
and is sampled four clock cycles before RSTOUT negates. The WKPCFG value configures the internal
weak pullup or weak pulldown pin characteristics after a reset occurs in the eMIOS or eTPU modules.
The value of WKPCFG is latched at reset, stored in the reset status register (SIU_RSR), and updated for
all reset sources except the debug port reset and software external reset. The WKPCFG value must be valid
and not change until RSTOUT negates.
6.2.1.6 External Interrupt Request Input (IRQ)
IRQ[0:15] The external interrupt request (IRQ) inputs connect to the SIU IRQ inputs. The external trigger
IRQ select register 1 (SIU_ETISR) specifies the IRQ[0:15] signals that are input to the SIU IRQs.
External interrupt requests are triggered by rising- and/or falling-edge events that are enabled by setting a
bit in:
• IRQ rising-edge event enable register (SIU_IREER)
• IRQ falling-edge event enable register (SIU_IFEER)
If the bit is set in both registers, both rising- and falling-edge events trigger an interrupt request. Each IRQ
has a counter that tracks the number of system clock cycles that occur between the rising- and falling-edge
events. An IRQ counter exists for each IRQ rising- or falling-edge event enable bit.
The digital filter length field in the IRQ digital filter register (SIU_IDFR) specifies the minimum number
of system clocks that the IRQ signal must hold a logic value to qualify the edge-triggered event as a valid
state change. When the number of system clocks in the IRQ counter equals the value in the digital filter
length field, the IRQ state latches and the IRQ counter is cleared.
If the previous filtered state of the IRQ does not match the current state, and the rising- or falling-edge
event is enabled, the IRQ flag bit is set to 1. For example, the IRQ flag bit is set if a rising-edge event
occurs under the following conditions:
• Previous filtered IRQ state was a logic 0
• Current latched IRQ state is a logic 1
• Rising-edge event is enabled for the IRQ
Table 6-4. BOOTCFG[0:1] Configuration
Value Meaning
0b00 Boot from internal flash memory (default)
0b01 FlexCAN / eSCI boot
0b10 Boot from external memory (no arbitration)
0b11 Boot from external memory (external arbitration)
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