Deserial Serial Peripheral Interface (DSPI)
MPC5566 Microcontroller Reference Manual, Rev. 2
Freescale Semiconductor 20-59
20.4.7.3 Modified Transfer Format Enabled (MTFE = 1) with
Classic SPI Transfer Format Cleared (CPHA = 0) for SPI and DSI
In the modified transfer format, the master and the slave sample later in the SCK period than in classic SPI
mode to allow for delays in device pads and board traces. These delays become a more significant fraction
of the SCK period as the SCK period decreases with increasing baud rates.
NOTE
For the modified transfer format to operate correctly, you must thoroughly
analyze the SPI link timing budget.
The master and the slave send data to the SOUTx pins when the PCSx signal asserts. After the PCSx to
SCKx delay elapses the first SCKx edge is generated. The slave samples the master SOUTx signal on every
odd numbered SCKx edge. The slave also sends more data on the slave SOUTx on every odd numbered
clock edge.
The master sends its second data bit to the SOUTx pin one system clock after the odd numbered SCKx
edge. The master samples the slave SOUTx pins by writing to the SMPL_PT field in the DSPIx_MCR.
Table 20-29 lists the number of system clock cycles (between the active-edge of SCKx and the master
sample point) for different values of the SMPL_PT bit field. The master sample point can be delayed by
one or two system clock cycles.
Table 20-29. Delayed Master Sample Point
SMPL_PT
Number of System Clock Cycles between
Odd-numbered Edge of SCK and Sampling of SIN
00 0
01 1
10 2
11 Invalid value
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