NXP Semiconductors MPC5566 - Low;MID Address Space Block Locking Register (FLASH_LMLR)

Flash Memory
MPC5566 Microcontroller Reference Manual, Rev. 2
Freescale Semiconductor 13-13
The flash does not allow you to write bits simultaneously that put the device into an illegal state. This is
implemented through a priority mechanism among the bits. The bit changing priorities are detailed in
Table 13-7.
If the user attempts to write two or more MCR bits simultaneously then only the bit with the highest
priority level is written. Setting two bits with the same priority level is prevented by existing write locks
and does not put the flash in an illegal state.
For example, setting FLASH_MCR[STOP] and FLASH_MCR[PGM] simultaneously results in only
FLASH_MCR[STOP] being set. Attempting to clear FLASH_MCR[EHV] while setting
FLASH_MCR[PSUS] results in FLASH_MCR[EHV] being cleared, while FLASH_MCR[PSUS]
remains unaffected.
13.3.2.2 Low/Mid Address Space Block Locking Register (FLASH_LMLR)
The low and mid address block locking register provides a means to protect blocks from being modified.
These bits along with bits in the secondary LMLOCK field (FLASH_SLMLR), determine if the block is
locked from program or erase. An “OR”’ of FLASH_LMLR and FLASH_SLMLR determine the final
lock status. Refer to Section 13.3.2.4, “Secondary Low/Mid Address Space Block Locking Register
(FLASH_SLMLR)” for more information on FLASH_SLMLR.
NOTE
In the event that blocks are not present (due to configuration or total
memory size), the LOCK bits defaults to locked, and are not writable. The
reset value is always 1 (independent of the shadow block), and register
writes have no effect.
Table 13-7. MCR Bit Set/Clear Priority Levels
Priority Level MCR Bits
1STOP
2ERS
3PGM
4EHV
5 ESUS, PSUS
Address: Base (0xC3F8_8000) + 0x0004 Access: R/W
0 12345678910 11 121314 1516171819202122232425262728293031
R LME 0 0 0 0 0 0 0 0 0 0
SLOCK
11
MLOCK
1111111111
LLOCK
W
Reset 0 0000000000 1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
The reset value of these bits is determined by flash values in the shadow row. Erasing the array sets the reset value to 1.
Figure 13-6. Low/Mid Address Space Block Locking Register (FLASH_LMLR)