Deserial Serial Peripheral Interface (DSPI)
MPC5566 Microcontroller Reference Manual, Rev. 2
20-36 Freescale Semiconductor
20.4.1.4 Debug Mode
The debug mode is used for system development and debugging. If the MCU enters debug mode while the
FRZ bit in the DSPIx_MCR is set, the DSPI stops all serial transfers and enters a stopped state. If the MCU
enters debug mode while the FRZ bit is cleared, the DSPI behavior is unaffected and remains dictated by
the module-specific mode and configuration of the DSPI. The DSPI enters debug mode when a debug
request is asserted by an external controller.
See Figure 20-18 for a state diagram.
20.4.2 Start and Stop of DSPI Transfers
The DSPI has two operating states: STOPPED and RUNNING. The states are independent of DSPI
configuration. The default state of the DSPI is STOPPED. In the STOPPED state no serial transfers are
initiated in master mode and no transfers are responded to in slave mode. The STOPPED state is also a
safe state for writing the various configuration registers of the DSPI without causing undetermined results.
The TXRXS bit in the DSPIx_SR is cleared in this state. In the RUNNING state, serial transfers take place.
The TXRXS bit in the DSPIx_SR is set in the RUNNING state.
Figure 20-18 shows a state diagram of the start and stop mechanism.
Figure 20-18. DSPI Start and Stop State Diagram
The transitions are described in Table 20-17.
Table 20-17. State Transitions for Start and Stop of DSPI Transfers
Transition # Current State Next State Description
0 RESET STOPPED Generic power-on-reset transition
1 STOPPED RUNNING The DSPI starts (transitions from STOPPED to RUNNING) when all
of the following conditions are true:
• EOQF bit is clear
• Debug mode is deselected or the FRZ bit is clear
• HALT bit is clear
2 RUNNING STOPPED The DSPI stops (transitions from RUNNING to STOPPED) after the
current frame for any one of the following conditions:
• EOQF bit is set
• Debug mode is selected and the FRZ bit is set
•HALT bit is set
RUNNING
TXRXS = 1
STOPPED
TXRXS = 0
RESET
Power-on-Reset 0
1
2
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