NXP Semiconductors MPC5566 - Clock Polarity Switching between DSPI Transfers

Deserial Serial Peripheral Interface (DSPI)
MPC5566 Microcontroller Reference Manual, Rev. 2
Freescale Semiconductor 20-63
20.4.7.6 Clock Polarity Switching between DSPI Transfers
To switch polarity between non-continuous DSPI frames, the edge generated by the change in the idle state
of the clock occurs one system clock before the chip select pin for the next frame asserts.
See Section 20.3.2.3, “DSPI Clock and Transfer Attributes Registers 0–7 (DSPIx_CTARn).”
In Figure 20-40, time ‘A’ shows the one clock interval. Time ‘B’ is programmable with a minimum of two
system clocks.
Figure 20-40. Polarity Switching between Frames
20.4.8 Continuous Serial Communications Clock
The DSPI provides the option of generating a continuous SCK signal for slave peripherals that require a
continuous clock.
Continuous SCK is enabled by setting the CONT_SCKE bit in the DSPIx_MCR. Continuous SCK is valid
in all configurations.
Continuous SCK is only supported for CPHA = 1. Setting CPHA = 0 is ignored if the CONT_SCKE bit is
set. Continuous SCK is supported for modified transfer format.
Clock and transfer attributes for the continuous SCK mode are set according to the following rules:
• When the DSPI is in SPI configuration, CTAR0 is used initially. At the start of each SPI frame
transfer, the CTAR specified by the CTAS for the frame is used.
• When the DSPI is in DSI configuration, the CTAR specified by the DSICTAS field is used at all
times.
• When the DSPI is in CSI configuration, the CTAR selected by the DSICTAS field is used initially.
At the start of an SPI frame transfer, the CTAR specified by the CTAS value for the frame is used.
At the start of a DSI frame transfer, the CTAR specified by the DSICTAS field is used.
• In all configurations, the currently selected CTAR remains in use until the start of a frame with a
different CTAR specified, or the continuous SCK mode is terminated.
The device is designed to use the same baud rate for all transfers made while using the continuous SCK.
Switching clock polarity between frames while using continuous SCK can cause errors in the transfer.
Continuous SCK operation is not guaranteed if the DSPI is put into module disable mode.
PCS
System clock
SCK
Frame 1
Frame 0
CPOL = 0 CPOL = 1
AB