NXP Semiconductors MPC5566 - Etpu Channel Interrupt Overflow Status Register (ETPU_CIOSR)

Enhanced Time Processing Unit (eTPU)
MPC5566 Microcontroller Reference Manual, Rev. 2
Freescale Semiconductor 18-35
18.4.5.3 eTPU Channel Interrupt Overflow Status Register (ETPU_CIOSR)
An interrupt overflow occurs when an interrupt is issued for a channel when the previous interrupt status
bit for the same channel has not been cleared. Interrupt overflow status from all channels are grouped in
ETPU_CIOSR. The bits are mirrored by the channels’ status/control registers. For information about
channel status registers and overflow, refer to Section 18.4.6.3, “eTPU Channel n Status Control Register
(ETPU_CnSCR),” and the eTPU Reference Manual.
NOTE
The host must write 1 to clear an interrupt overflow status bit.
Address: Base + 0x0000_0210 (eTPU A)
Address: Base + 0x0000_0214 (eTPU B)
Access: R/W1c
0123456789101112131415
RDTRS
31
DTRS
30
DTRS
29
DTRS
28
DTRS
27
DTRS
26
DTRS
25
DTRS
24
DTRS
23
DTRS
22
DTRS
21
DTRS
20
DTRS
19
DTRS
18
DTRS
17
DTRS
16
W
w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c
Reset0000000000000000
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
RDTRS
15
DTRS
14
DTRS
13
DTRS
12
DTRS
11
DTRS
10
DTRS
9
DTRS
8
DTRS
7
DTRS
6
DTRS
5
DTRS
4
DTRS
3
DTRS
2
DTRS
1
DTRS
0
W
w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c
Reset0000000000000000
Figure 18-15. eTPU Channel Data Transfer Request Status Register (ETPU_CDTRSR)
Table 18-16. ETPU_CDTRSR Field Descriptions
Field Description
0–31
DTRSn
Channel n data transfer request status.
0 Indicates that channel n has no pending data transfer request.
1 Indicates that channel n has a pending data transfer request.
To clear a status bit, the host must write 1 to it.
For details about data transfer requests refer to the eTPU Reference Manual.