NXP Semiconductors MPC5566 - Etpu Time Base 1 (TCR1) Visibility Register (ETPU_TB1 R)

Enhanced Time Processing Unit (eTPU)
MPC5566 Microcontroller Reference Manual, Rev. 2
18-30 Freescale Semiconductor
18.4.4.2 eTPU Time Base 1 (TCR1) Visibility Register (ETPU_TB1R)
This register provides visibility of the TCR1 time base for core host read access. This register is read-only.
The value of the TCR1 time base shown can be driven by the TCR1 counter or imported, depending on
the configuration set in ETPU_REDCR. For more information, refer to the eTPU Reference Manual.
Address: Base + 0x0000_0024 (eTPU A)
Address: Base + 0x0000_0044 (eTPU B)
Access: R/O
0123456789101112131415
R00000000 TCR1
W
Reset0000000000000000
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R TCR1
W
Reset0000000000000000
Figure 18-11. eTPU Time Base 1 (TCR1) Visibility Register (ETPU_TB1R)
Table 18-12. ETPU_TB1R Field Descriptions
Field Description
0–7 Reserved
8–31
TCR1
[0:23]
TCR1 value. Used on matches and captures. For more information, refer to the eTPU Reference Manual.