NXP Semiconductors MPC5566 - DSPI Receive FIFO Registers 0-3 (Dspix_Rxfrn)

Deserial Serial Peripheral Interface (DSPI)
MPC5566 Microcontroller Reference Manual, Rev. 2
Freescale Semiconductor 20-27
20.3.2.9 DSPI Receive FIFO Registers 0–3 (DSPIx_RXFRn)
The DSPIx_RXFRn registers provide visibility into the RX FIFO for debugging purposes. Each register is
an entry in the RX FIFO. The DSPIx_RXFR registers are read-only. Reading the DSPIx_RXFRn registers
does not alter the state of the RX FIFO. The device uses four registers to implement the RX FIFO, that is
DSPIx_RXFR0–DSPIx_RXFR3 are used.
The following table describes the field in the DSPI receive FIFO register:
Address:
Base + 0x007C (DSPIx_RXFR0)
Base + 0x0080 (DSPIx_RXFR1)
Base + 0x0084 (DSPIx_RXFR2)
Base + 0x0088 (DSPIx_RXFR3)
Access: R/O
0123456789101112131415
R0000000000000000
W
Reset0000000000000000
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
RRXDATA
W
Reset0000000000000000
Figure 20-11. DSPI Receive FIFO Registers 0–3 (DSPIx_RXFRn)
Table 20-11. DSPIx_RXFRn Field Description
Field Description
0–15 Reserved, must be cleared.
16–31
RXDATA
[15:0]
Receive data. Contains the received SPI data.