NXP Semiconductors MPC5566 - Translation Flow

e200z6 Core Complex
MPC5566 Microcontroller Reference Manual, Rev. 2
Freescale Semiconductor 3-15
The TLB is accessed indirectly through several MMU assist (MAS) registers. Software can read and write
to the MMU assist registers with mtspr (move to SPR) and mfspr (move from SPR) instructions. The
MMU registers contain information related to reading and writing an entry in the TLB. Data is read from
the TLB into the MAS registers with a tlbre (TLB read entry) instruction. Data is written to the TLB from
the MAS registers with a tlbwe (TLB write entry) instruction.
Refer to Section 3.3.1.5, “MMU Assist Registers (MAS[0:4], MAS[6]),” and the
e200z6 PowerPC
TM
Core Reference Manual for more details.
3.3.1.2 Translation Flow
The effective address, concatenated with the address space value of the MSR bit (MSR[IS] or MSR[DS]),
is compared to the number of bits of the EPN field and the TS field of TLB entries. If the contents of the
effective address plus the address space bit matches the EPN field and TS bit of the TLB entry, that TLB
entry is a candidate for a possible translation match. In addition to a match in the EPN field and TS, a
matching TLB entry must match with the current process ID of the access (in PID0), or have a TID value
of 0, indicating the entry is globally shared among all processes.
Figure 3-4 shows the translation match logic for the effective address plus its attributes, collectively called
the virtual address, and how it is compared with the corresponding fields in the TLB entries.
Figure 3-4. Virtual Address and TLB-Entry Compare Process
UX, UW, UR User execute, write, and read permission bits
WIMGE Translation attributes (Write-through required, cache-inhibited, memory coherence required, guarded, endian)
U0–U3 User bits—used by software only
IPROT Invalidation protect
VLE VLE page indicator
Table 3-2. TLB Entry Bit Definitions (continued)
Field Comments
TLB entry Hit
=0?
private page
shared page
=?
=?
TLB_entry[V]
TLB_entry[TS]
AS (from MSR[IS] or MSR[DS])
Process ID
TLB_entry[TID]
TLB_entry[EPN]
EA page number bits
=?