NXP Semiconductors MPC5566 - RAM ECC Master Number Register (ECSM_REMR)

Error Correction Status Module (ECSM)
MPC5566 Microcontroller Reference Manual, Rev. 2
8-12 Freescale Semiconductor
8.2.1.12 RAM ECC Master Number Register (ECSM_REMR)
The REMR is an 8-bit register for capturing the XBAR bus master number of the last, correctly-enabled
ECC event in the RAM memory. Depending on the state of the ECSM_ECR, an ECC event in the RAM
loads the address, attributes and data of the access into the ECSM_REAR, ECSM_REMR, ECSM_REAT
and ECSM_REDR registers, and asserts the RNCE flag in ECSM_ESR.
8.2.1.13 RAM ECC Attributes Register (ECSM_REAT)
The ECSM_REAT is an 8-bit register for capturing the XBAR bus master attributes of the last,
correctly-enabled ECC event in the RAM memory. Depending on the state of the ECSM_ECR, an ECC
event in the RAM loads the address, attributes and data of the access into the ECSM_REAR,
ECSM_REMR, ECSM_REAT and ECSM_REDR registers, and asserts the RNCE flag in ECSM_ESR.
Table 8-10. ECSM_REAR Field Descriptions
Field Description
0–31
REAR
[0:31]
RAM ECC address. Contains the faulting access address of the last, correctly-enabled RAM ECC event. The reset
value of this field is undefined.
Base + 0x0066 Access: Read
01234567
R0000 REMR
W
Reset
1
0 0 0 0UUUU
1
“U” signifies a bit that is uninitialized.
Figure 8-10. RAM ECC Master Number Register (ECSM_REMR)
Table 8-11. ECSM_REMR Field Descriptions
Field Description
0–3 Reserved.
4–7
REMR
[0:3]
RAM ECC master number. Contains the XBAR bus master number of the faulting access of the last,
correctly-enabled RAM ECC event. The reset value of this field is undefined.