MPC5566 Microcontroller Reference Manual, Rev. 2
Freescale Semiconductor 22-33
After exiting freeze mode, FlexCAN2 tries to re-synchronize to the CAN bus by waiting for 11 consecutive
recessive bits.
22.4.6.2 Module Disabled Mode
This low power mode is entered when the CANx_MCR[MDIS] bit is asserted. If the module is disabled
during freeze mode, it shuts down the clocks to the CPI and MBM sub-modules, sets the
CANx_MCR[MDISACK] bit and negates the CANx_MCR[FRZACK] bit.
If the module is disabled during transmission or reception, FlexCAN2 completes the following sequence:
1. Waits to enter the idle or bus off state, or waits for the third bit of the intermission and checks to
determine if the bit is recessive.
2. Waits for all internal activities, like move-in or move-out, to finish.
3. Ignores the RX input pin and drives the TX pin as recessive.
4. Shuts down the clocks to the CPI and MBM sub-modules.
5. Sets the NOTRDY and MDISACK bits in CANx_MCR.
The bus interface unit continues to operate by enabling the CPU to access memory mapped registers except
the free running timer, CANx_ECR, and the message buffers, which cannot be accessed when the module
is disabled. To exit this mode, negate the CANx_MCR[MDIS] bit, which resumes the clocks and negates
the CANx_MCR[MDISACK] bit.
22.4.7 Interrupts
The module can generate interrupts from 20 interrupt sources (16 interrupts due to message buffers, one
interrupt due to an error condition, two interrupts for the OR'd MB16–MB31 and MB32–63, and one
interrupt for one of the following: a bus off condition, a transmit warning, or a receive warning).
Each of the 64 message buffers can be an interrupt source, if its corresponding CANx_IMRH or
CANx_IMRL bit is set. There is no distinction between TX and RX interrupts for a particular buffer, under
the assumption that the buffer is initialized for either transmission or reception. Each of the buffers has
assigned a flag bit in the CANx_IFRH or CANx_IFRL registers. The bit is set when the corresponding
buffer completes a successful transmission/reception and is cleared when the CPU writes it to 1.
A combined interrupt for each of two MB groups, MB16–MB31 and MB32–MB63, is also generated by
an OR of all the interrupt sources from the associated MBs. This interrupt gets generated when any of the
MBs generates an interrupt. In this case the CPU must read the CANx_IFRH and CANx_IFRL registers
to determine which MB caused the interrupt.
The other two interrupt sources (bus off/transmit warning/receive warning and error) generate interrupts
like the MB interrupt sources, and can be read from CANx_ESR. The bus off/transmit warning/receive
warning and error interrupt mask bits are located in the CANx_CR.
To Next Page
Loading...
