System Integration Unit (SIU)
MPC5566 Microcontroller Reference Manual, Rev. 2
Freescale Semiconductor 6-117
The following table describes the external clock control fields:
6.3.1.166 Compare A Register High (SIU_CARH)
The compare registers are not intended for general application use, but are used temporarily by the BAM
during boot and intended optionally for communication with calibration tools. After reset, calibration tools
can immediately write a non-zero value to these registers. The application code, using the registers then as
read only, can read them to determine if a calibration tool is attached and operate appropriately.
The compare registers can be used just like 128 bits of memory mapped RAM that is always 0 out of reset,
or they can perform a 64-bit to 64-bit compare. The compare function is continuous (combinational logic
— not requiring a start or stop). The compare result appears in the MATCH bit in the SIU_CCR register.
Table 6-154. SIU_ECCR Field Descriptions
Bits Name Description
0–17 — Reserved
18–23 ENGDIV
[0:5]
Engineering clock division factor. Specifies the frequency ratio between the system clock
and ENGCLK. The ENGCLK frequency is divided from the system clock frequency
according to the following equation:
The maximum ENGCLK frequency is 72 MHz (144 MHz
÷ 2)
Note: Clearing ENGDIV to 0 is the reset setting. Synchronization between ENGCLK and
CLKOUT cannot be guaranteed when ENGDIV is 0.
24–27 — Reserved
28 EBTS External bus tap select. Changes the phase relationship between the system clock and
CLKOUT. Changing the phase relationship so that CLKOUT is advanced in relation to the
system clock increases the output hold time of the external bus signals to a non-zero value.
It also increases the output delay times, increases the input hold times to non-zero values,
and decreases the input setup times. Refer to the Electrical Specifications for how the
EBTS bit affects the external bus timing.
0 External bus signals have zero output hold times.
1 External bus signals have non-zero output hold times.
Note: Do not change EBTS while an external bus transaction is in process.
29 — Reserved
30–31 EBDF
[0:1]
External bus division factor. Specifies the frequency ratio between the system clock and
the external clock, CLKOUT. Do not change EBDF during an external bus access or while
an access is pending. The CLKOUT frequency is divided from the system clock frequency
according to the descriptions below. When operating in dual controller mode (1:1), set the
divider to 0b01 (divide-by-2).
00 Invalid value
01 Divide by 2
10 Invalid value
11 Divide by 4
Engineering clock frequency
System clock frequency
ENGDIV 2×
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