NXP Semiconductors MPC5566 - Emios Alternate Address Register (Emios_Altan)

Enhanced Modular Input/Output Subsystem (eMIOS)
MPC5566 Microcontroller Reference Manual, Rev. 2
17-22 Freescale Semiconductor
17.3.1.9 eMIOS Alternate Address Register (EMIOS_ALTAn)
The EMIOS_ALTAn register provides an alternate read-only address to access channel registers in PEC
and WPTA modes. If EMIOS_ALTAn is used it is possible to access the A2 register in the PEC and WPTA
modes. The EMIOS_ALTAn address register does not implement coherency mechanisms such as the
blocking of B register updates after the A register is read.
Table 17-8, “EMIOS_CADRn, EMIOS_CBDRn, and EMIOS_ALTAn Value Assignments,” shows the
internal registers accessed by address EMIOS_ALTAn in each one of the channel operation modes.
The following table describes the field in the eMOIS alternate address register:
17.4 Functional Description
The eMIOS provides independent channels (UC) that can be configured and accessed by the MCU. Four
time bases can be shared by the channels through four counter buses and each unified channel can generate
its own time base. Optionally, the counter A bus can be driven by an external time base from the eTPU
imported through the STAC interface.
NOTE
Counter bus A can be driven by unified channel 23 or by the STAC bus.
Counter bus B, C, and D are driven by unified channels 0, 8, and 16,
respectively. Counter bus A can be shared among all unified channels. UCs
0 to 7 can share counter bus A and B, UCs 8 to 15 can share counter bus A
and C, and UCs 16 to 23 can share counter buses A and D.
Address: UCn Base + 0x0014 Access: R/W
0123456789101112131415
R00000000 ALTA[8:15]
W
Reset00000000000000 0 0
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R ALTA[16:31]
W
Reset00000000000000 0 0
Figure 17-10. eMIOS Alternate Address Register (EMIOS_ALTAn)
Table 17-12. EMIOS_ALTAn Field Descriptions
Field Description
0–7 Reserved.
8–31
ALTA
Alternate address. Set when an alternate address is provided for accessing both the A1 and A2 channel
registers.
0 Access only A1 register
1 Access both A1 and A2 registers