NXP Semiconductors MPC5566 - FMPLL and Clock Architecture

Frequency Modulated Phase Locked Loop and System Clocks (FMPLL)
MPC5566 Microcontroller Reference Manual, Rev. 2
11-2 Freescale Semiconductor
11.1.1.1 FMPLL and Clock Architecture
Figure 11-1. FMPLL Block and Clock Architecture
EXTAL_EXTCLK
PFD/
charge
Filter RFD
Bus interface
Control/status
registers
Successive
approximation
frequency
FM
control
1
0
pumps
Current
controlled
oscillator
(ICO)
XTAL
0
1
MFD
PLLCFG[0:1]
MDIS
DSPI
MCKO_EN
MCKO_GT
MCKO
divider
MCKO
MDIS
EBI
MDIS
eMIOS
MDIS
eTPU engines
MDIS
eSCI
MDIS
CAN interface CLK
FlexCAN
CLK_SRC
Message buffer CLK
ENGCLK
divider
CLKOUT
divider
ENGCLK
CLKOUT
NPC
PLLREF
PLLSEL
MODE
Core, INTC, eDMA, SIU, BAM,
RAMs, eQADC, flash, XBAR,
PBRIDGE_A, PBRIDGE_B
Oscillator clock
SIU
System
clock
1
0
PLL
NOTE: The clock mode selection
and associated package pin settings
and FMPLL_SYNSR settings are
displayed in Table 11-1.
OSC PREDIV